Soft Reset (Sreset); Invalidation Request (Inv); Hitm# Vs. Other Intel; Inv Vs. Other Intel ® Quark Core Signals - Intel Quark SoC X1000 Core Developer's Manual

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Hardware Interface—Intel
Table 52.

HITM# vs. Other Intel

Pin Symbol
EADS#
HLDA, BOFF#
ADS#, CACHE#
9.2.17.4

Soft Reset (SRESET)

When in Enhanced Bus mode, SRESET has the following differences: SRESET, unlike
RESET, does not cause the AHOLD, A20M#, FLUSH#, RESERVED#, and WB/WT# pins
to be sampled (i.e., special test modes and on-chip cache configuration cannot be
accessed with SRESET.)
Note: The implementation of Intel
A20M# pin; it is tied to 1'b1.
On SRESET, the internal SMRAM base register retains its previous value and the
processor does not flush, write-back or disable the internal cache. CR0.CD and CR0.NW
retain previous values, CR0.4 is set to 1, and the remaining bits are cleared. Because
SRESET is treated as an interrupt, it is possible to have a bus cycle while SRESET is
asserted. A bus cycle could be due to an on-going instruction, emptying the write
buffers of the processor, or snoop write-back cycles if there is a snoop hit to an M-state
line while SRESET is asserted.
Note: For both Standard Bus mode and Enhanced Bus mode:
• SMI# must be blocked during SRESET. It must also be blocked for a minimum of
two clocks after SRESET is de-asserted.
• SRESET must be blocked during SMI#. It must also be blocked for a minimum of 20
clocks after SMIACT# is de-asserted.
9.2.17.5

Invalidation Request (INV)

INV is a cache coherency protocol pin that is used only in Enhanced Bus mode. It is
sampled by the processor on EADS#-driven snoop cycles. It is necessary to assert this
pin to simulate the Standard mode processor invalidate cycle on write-through-only
lines. INV also invalidates the write-back lines. However, when the snooped line is in
the M-state, the line is written back and then invalidated.
INV is sampled when EADS# is asserted. When INV is not asserted with EADS#, the
snoop cycle has no effect on a write-through-only line or on a line allocated as write-
back but not yet modified. If the line is write-back and modified, it is written back to
memory but is not de-allocated (invalidated) from the internal cache. The address of
the snooped cache line is provided on the address bus (see
Table 53. INV vs. Other Intel
Pin Symbol
EADS#
A[31:4]
October 2013
Order Number: 329679-001US
Quark Core
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Quark Core Signals
HITM# is asserted due to an EADS#-driven snoop, provided the snooped line is in the
M-state in the cache.
HITM# does not float under these signals.
The beginning of a snoop write-back cycle is identified by the assertion of ADS#,
CACHE#, and HITM#.
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Quark Core on Intel
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Quark Core Signals
EADS# determines when INV is sampled.
The address of the snooped cache line is provided on these pins.
Relation To This Signal
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Quark SoC X1000 does not use the
Table
Relation To This Signal
53).
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Intel Quark SoC X1000 Core
Developer's Manual
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