Page Cacheability - Intel Quark SoC X1000 Core Developer's Manual

®
On-Chip Cache—Intel Quark Core
Figure 52.

Page Cacheability

7.6.1 Write-Back Enhanced Intel
Processor Page Cacheability
In Write-Back Enhanced Intel
processor and the system hardware must determine the cacheability and the
configuration (write-back or write-through) on a line-by-line basis. The system
hardware's cacheability is determined by KEN# and the configuration by WB/WT#. The
processor's indication of cacheability is determined by PCD and the configuration by
PWT. The PWT bit controls the write policy for the second-level caches used with the
Write-Back Enhanced Intel
through policy for the current page, while clearing PWT to 0 defines a write-back policy
for the current page.
October 2013
Order Number: 329679-001US
C N
CR0
D W
Cache Control Logic
Cache Memory
31 22
Directory
Table
Linear
Address
10 10
31 0
31
CR0
CR1
+
PCD, PWT
CR2
CR3 PCD, PWT
Directory
Control Registers
®
Quark SoC X1000 Core-based systems, both the
®
Quark SoC X1000 Core. Setting PWT to 1 defines a write-
12 0
Offset
PCD
31 0
0
PCD, PWT
+
Page Table
(From CR0)
®
Quark SoC X1000 Core and
FLUSH#
KEN#
PCD
PWT
CD
®
Intel Quark SoC X1000 Core
Developer's Manual
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