Stop Clock Snoop State (Cache Invalidations); Auto Halt Power Down Flush State (Cache Flush) For The Write-Back Enhanced Intel Quark Soc X1000 Core - Intel Quark SoC X1000 Core Developer's Manual

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Hardware Interface—Intel
in this state, the FLUSH# is serviced by transitioning to the Stop Clock Flush state.
After the FLUSH# is completed, the processor returns to the Auto HALT Power Down
state.
The system can generate a STPCLK# while the processor is in the Auto HALT Power
Down state. The processor then generates a Stop Grant bus cycle and enters the Stop
Grant state from the Auto HALT Power Down state. When the system de-asserts the
STPCLK# interrupt, the processor returns to the Auto HALT Power Down state. The
processor does not generate a new HALT bus cycle when it re-enters the Auto HALT
Power Down state from the Stop Grant state.
9.6.6

Stop Clock Snoop State (Cache Invalidations)

When the processor is in the Stop Grant state or the Auto HALT Power Down state, the
processor recognizes HOLD, AHOLD, BOFF#, and EADS# for cache invalidation. When
the system asserts HOLD, AHOLD, or BOFF#, the processor floats the bus accordingly.
When the system asserts EADS#, the processor transparently enters the Stop Clock
Snoop state and powers up in order to perform the required cache snoop cycle and
write-back cycles. It then refreezes the CLK to the processor core and returns to the
previous state (i.e., either the Stop Grant state or the Auto HALT Power Down state).
The processor does not generate a bus cycle when it returns to the previous state.
9.6.6.1 Auto HALT Power Down Flush State (Cache Flush) for the Write-Back
Enhanced Intel
When the Write-Back Enhanced Intel
Enhanced Bus mode, and a FLUSH# event occurs during Auto HALT Power Down state,
the processor transitions to the Auto HALT Power Down Flush state. If the on-chip
cache is configured as a write-back cache, the CLK to the processor core is turned on
until all the dirty lines are written back, the cache is invalidated, and the two flush
acknowledge cycles are completed. If the on-chip cache is configured as a write-
through cache, the CLK to the processor core is turned on until the cache is invalidated.
The processor then refreezes the CLK and returns to the previous state (i.e., the Auto
HALT Power Down state). Auto HALT Power Down Flush state is entered only from the
Auto HALT Power Down state and not from the Stop Grant state.
October 2013
Order Number: 329679-001US
Quark Core
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Quark SoC X1000 Core
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Quark SoC X1000 Core is in either Standard or
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Intel Quark SoC X1000 Core
Developer's Manual
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