Burst Mode Details; Adding Wait States To Burst Cycles; Effect Of Changing Ken - Intel Quark SoC X1000 Core Developer's Manual

®
Bus Operation—Intel Quark Core
Figure 92.

Effect of Changing KEN#

CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
A3–A2
BE3#–BE0#
RDY#
KEN#
BLAST#
DATA
10.3.4

Burst Mode Details

10.3.4.1

Adding Wait States to Burst Cycles

Burst cycles need not return data on every clock. The Intel
strobes data into the chip only when either RDY# or BRDY# is asserted. Deasserting
BRDY# and RDY# adds a wait state to the transfer. A burst cycle where two clocks are
required for every burst item is shown in
October 2013
Order Number: 329679-001US
Ti T1
†
To Processor
T2 T2 T2
®
Figure 93.
T1 T2 T2
† †
242202-037
Quark SoC X1000 Core
®
Intel Quark SoC X1000 Core
Developer's Manual
205