Differences Between 16- And 32-Bit Addresses; Data Types; Base And Index Registers For 16- And 32-Bit Addresses - Intel Quark SoC X1000 Core Developer's Manual

3.5.4

Differences Between 16- and 32-Bit Addresses

In order to provide software compatibility with older processors, the Intel
X1000 Core can execute 16-bit instructions in Real and Protected Modes. The processor
determines the size of the instructions it is executing by examining the D bit in the CS
segment Descriptor. If the D bit is 0 then all operand lengths and effective addresses
are assumed to be 16 bits long. If the D bit is 1 then the default length for operands
and addresses is 32 bits. In Real Mode the default size for operands and addresses is
16-bits.
Regardless of the default precision of the operands or addresses, the Intel
X1000 Core is able to execute either 16- or 32-bit instructions. This is specified via the
use of override prefixes. Two prefixes, the Operand Size Prefix and the Address Length
Prefix, override the value of the D bit on an individual instruction basis. These prefixes
are automatically added by Intel assemblers.
Example: The Intel
programmer needs to access the EAX registers. The assembler code for this might be
MOV EAX, 32-bit MEMORY OP. The Macro Assembler automatically determines that an
Operand Size Prefix is needed and generates it.
Example: The D bit is 0, and the programmer wishes to use Scaled Index addressing
mode to access an array. The Address Length Prefix allows the use of MOV DX,
TABLE[ESI*2]. The assembler uses an Address Length Prefix because, with D=0, the
default addressing mode is 16-bits.
Example: The D bit is 1, and the program wants to store a 16-bit quantity. The Operand
Length Prefix is used to specify only a 16-bit value; MOV MEM16, DX.
The OPERAND LENGTH and Address Length Prefixes can be applied separately or in
combination to any instruction. The Address Length Prefix does not allow addresses
over 64 Kbytes to be accessed in Real Mode. A memory address which exceeds FFFFH
will result in a General Protection Fault. An Address Length Prefix only allows the use of
the additional Intel
When executing 32-bit code, the Intel
displacements, and any register can be used as base or index registers. When
executing 16-bit code, the displacements are either 8, or 16 bits, and the base and
index register are as listed in
Table 4.

BASE and INDEX Registers for 16- and 32-Bit Addresses

BASE REGISTER
INDEX REGISTER
SCALE FACTOR
DISPLACEMENT
3.6

Data Types

3.6.1 Data Types
The Intel
following descriptions, the processor consists of the base architecture registers.
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Intel Quark SoC X1000 Core
Developer's Manual
28
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Quark SoC X1000 Core is executing in Real Mode and the
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Quark SoC X1000 Core addressing modes.
Table 4
16-Bit Addressing
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Quark SoC X1000 Core can support a wide-variety of data types. In the
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Intel Quark Core—Architectural Overview
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Quark SoC X1000 Core uses either 8-, or 32-bit
below.
BX,BP Any 32-bit GP Register
SI,DI Any 32-bit GP Register Except ESP
none 1, 2, 4, 8
0, 8, 16 bits 0, 8, 32 bits
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Quark SoC
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Quark SoC
32-Bit Addressing
October 2013
Order Number: 329679-001US