Intel Quark SoC X1000 Core Developer's Manual page 269

Instruction Set Summary—Intel
Table 89. Clock Count Summary (Sheet 3 of 13)
Instruction
TEST = Logical Compare
reg1 and reg2
memory and register
immediate and register
immediate and acc.
immediate and memory
MUL = Multiply (unsigned)
acc. with register
Multiplier-Byte
Word
Dword
acc. with memory
Multiplier-Byte
Word
Dword
IMUL = Integer Multiply (unsigned)
acc. with register
Multiplier-Byte
Word
Dword
acc. with memory
Multiplier-Byte
Word
Dword
reg1 with reg2
Multiplier-Byte
Word
Dword
register with memory
Multiplier-Byte
Word
Dword
reg1 with imm. to reg2
Multiplier-Byte
Word
Dword
mem. with imm. to reg.
Multiplier-Byte
Word
Dword
Note: See
October 2013
Order Number: 329679-001US
®
Quark Core
1000 010w : 11 reg1 reg2
1000 010w : mod reg r/m
1111 011w : 11 000 reg : immediate data
1010100w : immediate data
1111 011w : mod 000 r/m : immediate
data
1111 011w : 11 100 reg
1111 011w : mod 100 r/m
1111 011w : 11 101 reg
1111 011w : mod 101 r/m
0000 1111 : 10101111 : 11 reg1 reg2
0000 1111 : 10101111 : mod reg r/m
0110 10s1 : 11 reg1 reg2 : immediate
data
0110 10s1 : mod reg r/m : immediate
data
Table 92 for notes and abbreviations for items in this table.
Cache
Format
13/18
13/26
13/42
13/18
13/26
13/42
13/18
13/26
13/42
13/18
13/26
13/42
13/18
13/26
13/42
13/18
13/26
13/42
13/18
13/26
13/42
13/18
13/26
13/42
Penalty
if
Notes
Hit Cache
Miss
1
2 2
1
1
2 2
MN/MX,3
MN/MX,3
MN/MX,3
1 MN/MX,3
1 MN/MX,3
1 MN/MX,3
MN/MX,3
MN/MX,3
MN/MX,3
MN/MX,3
MN/MX,3
MN/MX,3
MN/MX,3
MN/MX,3
MN/MX,3
1 MN/MX,3
1 MN/MX,3
1 MN/MX,3
MN/MX,3
MN/MX,3
MN/MX,3
MN/MX,3
MN/MX,3
MN/MX,3
®
Intel Quark SoC X1000 Core
Developer's Manual
269