Quark Soc X1000 Core; 1Floating-Point Exceptions - Intel Quark SoC X1000 Core Developer's Manual

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Bus Operation—Intel Quark Core
10.3.14 Floating-Point Error Handling for the Intel
Core
The Intel
errors. The simplest method is to raise interrupt 16 whenever an unmasked floating-
point error occurs. This option may be enabled by setting the NE bit in control register
0 (CR0).
The Intel
hardware to determine how floating-point errors are reported. This option is necessary
for compatibility with the error reporting scheme used in DOS-based systems. The NE
bit must be cleared in CR0 to enable user-defined error reporting. User-defined error
reporting is the default condition because the NE bit is cleared on reset.
Two pins, floating-point error (FERR#, an output) and ignore numeric error (IGNNE#,
an input) are provided to direct the actions of hardware if user-defined error reporting
is used. The Intel
floating-point error has occurred.
Note: The implementation of Intel
capability to control the IGNNE# pin via a register; the default value of the register is
1'b0.
In some cases FERR# is asserted when the next floating-point instruction is
encountered, and in other cases it is asserted before the next floating-point instruction
is encountered, depending upon the execution state of the instruction causing the
exception.
10.3.14.1 Floating-Point Exceptions
The following class of floating-point exceptions drive FERR# at the time the exception
occurs (i.e., before encountering the next floating-point instruction).
1. The stack fault, invalid operation, and denormal exceptions on all transcendental
instructions, integer arithmetic instructions, FSQRT, FSEALE, FPREM(1), FXTRACT,
FBLD, and FBSTP.
2. Any exceptions on store instructions (including integer store instructions).
The following class of floating-point exceptions drive FERR# only after encountering the
next floating-point instruction.
1. Exceptions other than on all transcendental instructions, integer arithmetic
instructions, FSQRT, FSCALE, FPREM(1), FXTRACT, FBLD, and FBSTP.
2. Any exception on all basic arithmetic, load, compare, and control instructions (i.e.,
all other instructions).
Note: The implementation of Intel
capability to control the IGNNE# pin via a register; the default value of the register is
1'b0.
IGNNE# is an input to the Intel
cleared, and IGNNE# is asserted, the Intel
floating-point errors and continue executing floating-point instructions. When IGNNE#
is deasserted, the IGNNE# is an input to these processors that freeze on floating-point
instructions that get errors (except for the control instructions FNCLEX, FNINIT,
FNSAVE, FNSTENV, FNSTCW, FNSTSW, FNSTSW AX, FNENI, FNDISI and FNSETPM).
IGNNE# may be asynchronous to the Intel
October 2013
Order Number: 329679-001US
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Quark SoC X1000 Core provides two options for reporting floating-point
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Quark SoC X1000 Core also provides the option of allowing external
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Quark SoC X1000 Core asserts the FERR# output to indicate that a
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Quark Core on Intel
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Quark Core on Intel
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Quark SoC X1000 provides the
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Quark SoC X1000 provides the
Quark SoC X1000 Core. When the NE bit in CR0 is
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Quark SoC X1000 Core ignores user
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Quark SoC X1000 Core clock.
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Quark SoC X1000
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Intel

Quark SoC X1000 Core

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