Pae Paging; Pdpte Registers; Use Of Cr3 With Pae Paging - Intel Quark SoC X1000 Core Developer's Manual

Protected Mode Architecture—Intel
CR4.PGE enables global pages. If CR4.PGE = 0, no translations are shared across
address spaces; if CR4.PGE = 1, specified translations may be shared across address
spaces.
CR4.SMEP allows pages to be protected from supervisor-mode instruction fetches. If
CR4.SMEP = 1, software operating in supervisor mode cannot fetch instructions from
linear addresses that are accessible in user mode.
IA32_EFER.NXE enables execute-disable access rights for PAE paging. If
IA32_EFER.NXE = 1, instructions fetches can be prevented from specified linear
addresses (even if data reads from the addresses are allowed).
6.4.3

PAE Paging

A logical processor uses PAE paging if CR0.PG = 1 and CR4.PAE = 1
With PAE paging, a logical processor maintains a set of four (4) PDPTE registers, which
are loaded from an address in CR3. Linear address are translated using 4 hierarchies of
in-memory paging structures, each located using one of the PDPTE registers. (This is
different from the other paging modes, in which there is one hierarchy referenced by
CR3.)
6.4.3.1

PDPTE Registers

When PAE paging is used, CR3 references the base of a 32-Byte page-directory-pointer
table. Table 29
Table 29.

Use of CR3 with PAE Paging

Bit Position(s)
4:0
31:5
The page-directory-pointer-table comprises four (4) 64-bit entries called PDPTEs. Each
PDPTE controls access to a 1-GByte region of the linear-address space. Corresponding
to the PDPTEs, the logical processor maintains a set of four (4) internal,
non-architectural PDPTE registers, called PDPTE0, PDPTE1, PDPTE2, and PDPTE3.
The logical processor loads these registers from the PDPTEs in memory as part of
certain operations:
• If PAE paging would be in use following an execution of MOV to CR0 or MOV to CR4
and the instruction is modifying any of CR0.CD, CR0.NW, CR0.PG, CR4.PAE,
CR4.PGE, CR4.PSE, or CR4.SMEP; then the PDPTEs are loaded from the address in
CR3.
• If MOV to CR3 is executed while the logical processor is using PAE paging, the
PDPTEs are loaded from the address being loaded into CR3.
• If PAE paging is in use and a task switch changes the value of CR3, the PDPTEs are
loaded from the address in the new CR3 value.
Table 30
and any reserved bit, the MOV to CR instruction causes a general-protection exception
(#GP(0)) and the PDPTEs are not loaded. As shown in
63:MAXPHYADDR are reserved in the PDPTEs.
October 2013
Order Number: 329679-001US
®
Quark Core
illustrates how CR3 is used with PAE paging.
Ignored
Physical address of the 32-Byte aligned page-directory-pointer table used for
linear-address translation
gives the format of a PDPTE. If any of the PDPTEs sets both the P flag (bit 0)
Contents
Table 30, bits 2:1, 8:5, and
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Intel Quark SoC X1000 Core
Developer's Manual
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