Page Level Protection (R/W, U/S Bits) - Intel Quark SoC X1000 Core Developer's Manual

— The I/D bit of the page fault error code (bit 4) will be set when an instruction
page faults occurs and CR4.SMEP. It may also be set in other cases.
• CR4.SMEP is zero by default: set to zero on RESET
• CPUID >3 <8000_0000 are visible only when IA32_MISC_ENABLES.BOOT_NT4[22]
= 1'b0.
• Requires supporting IA32_MISC_ENABLE Model Specific Register (MSR).
6.4.5.1.1 Instruction Fetches Access Rights in Supervisor Mode (CPL <3)
For 32-bit paging when IA32_EFER.NXE = 0, access rights depend on the value of
CR4.SMEP:
• If CR4.SMEP = 0, instructions may be fetched from any linear address with a valid
translation.
• If CR4.SMEP = 1, instructions may be fetched from any linear address with a valid
translation for which the U/S flag (bit 2) is 0 in at least one of the paging-structure
entries controlling the translation.
For PAE paging with IA32_EFER.NXE = 1, access rights depend on the value of
CR4.SMEP:
• If CR4.SMEP = 0, instructions may be fetched from any linear address with a valid
translation for which the XD flag (bit 63) is 0 in every paging-structure entry
controlling the translation. If XD flag is set Page Fault is generated.
• If CR4.SMEP = 1, instructions may be fetched from any linear address with a valid
translation for which the U/S flag is 0 in at least one of the paging-structure entries
controlling the translation; and the XD flag is 0 in every paging-structure entry
controlling the translation.
6.4.5.1.2 Instruction Fetches Access Rights in User Mode (CPL=3)
For 32-bit paging when IA32_EFER.NXE = 0, instructions may be fetched from any
linear address with a valid translation for which the U/S flag is 1 in every paging-
structure entry controlling the translation.
For PAE paging with IA32_EFER.NXE = 1, instructions may be fetched from any linear
address with a valid translation for which the U/S flag is 1 and the XD flag is 0 in every
paging-structure entry controlling the translation.
6.4.6

Page Level Protection (R/W, U/S Bits)

The Intel
systems. The paging mechanism distinguishes between two levels of protection: user,
which corresponds to level 3 of the segmentation based protection; and supervisor,
which encompasses all of the other protection levels (0, 1, 2).
The R/W and U/S bits are used in conjunction with the WP bit in the flags register
(EFLAGS). The WP bit is used by the Intel
pages from supervisor write accesses. When WP=0, the supervisor can write to a read-
only page as defined by the U/S and R/W bits. When WP=1, supervisor access to a
read-only page (R/W=0) causes a page fault (exception 14).
Table 34
WP=0, the supervisor can write to pages regardless of the state of the R/W bit. When
WP=1 and R/W=0, the supervisor cannot write to a read-only page. A user attempt to
access a supervisor-only page (U/S=0) or to write to a read-only page causes a page
fault (exception 14).
®
Intel Quark SoC X1000 Core
Developer's Manual
102
®
Quark SoC X1000 Core provides a set of protection attributes for paging
shows the affect of the WP, U/S and R/W bits on accessing memory. When
®
Intel Quark Core—Protected Mode Architecture
®
Quark SoC X1000 Core to protect read-only
Order Number: 329679-001US
October 2013