Processor Environment; Transition To And From System Management Mode - Intel Quark SoC X1000 Core Developer's Manual

System Management Mode (SMM) Architectures—Intel
Figure 58.

Transition to and from System Management Mode

Reset
Note: Reset could occur by asserting the RESET or SRESET pin.
The external signal SMI# causes the processor to switch to SMM. The RSM instruction
exits SMM. SMM is transparent to applications programs and operating systems
because of the following:
• The only way to enter SMM is via a type of non-maskable interrupt triggered by an
external signal.
• The processor begins executing SMM code from a separate address space, called
system management RAM (SMRAM).
• Upon entry into SMM, the processor saves the register state of the interrupted
program in a part of SMRAM called the SMM context save space.
• All interrupts normally handled by the operating system or by applications are
disabled upon entry into SMM.
• A special instruction, RSM, restores processor registers from the SMM context save
space and returns control to the interrupted program.
SMM is similar to Real Mode in that there are no privilege levels or address mapping. An
SMM program can execute all I/O and other system instructions and can address up to
4 Gbytes of memory.
8.4.2

Processor Environment

When an SMI# signal is recognized on an instruction execution boundary, the processor
waits for all stores to complete, including emptying of the write buffers. The final write
cycle is complete when the system returns RDY# or BRDY#. The processor then drives
SMIACT# active, saves its register state to SMRAM space, and begins to execute the
SMM handler.
SMI# has greater priority than debug exceptions and external interrupts. This means
that if more than one of these conditions occur at an instruction boundary, only the
SMI# processing occurs, not a debug exception or external interrupt. Subsequent
SMI# requests are not acknowledged while the processor is in SMM. The first SMI#
interrupt request that occurs while the processor is in SMM is latched and serviced
when the processor exits SMM with the RSM instruction. The processor latches only one
SMI# while it is in SMM.
October 2013
Order Number: 329679-001US
®
Quark Core
Real Mode
Reset or RSM
Reset or
PE=1
PE=0
SMI#
Protected Mode
RSM
VM=0 VM=1
RSM
Virtual - 86 Mode
SMI#
System
Management
Mode
SMI#
A5234-01
®
Intel Quark SoC X1000 Core
Developer's Manual
135