Quark Soc X1000 Core Floating-Point Error Handling In; Enhanced Bus Mode Operation For The Write-Back Enhanced Intel Quark Soc X1000 Core; At-Compatible Systems; Quark Soc X1000 - Intel Quark SoC X1000 Core Developer's Manual

In systems with user-defined error reporting, the FERR# pin is connected to the
interrupt controller. When an unmasked floating-point error occurs, an interrupt is
raised. If IGNNE# is high at the time of this interrupt, the Intel
Core freezes (disallowing execution of a subsequent floating-point instruction) until the
interrupt handler is invoked. By driving the IGNNE# pin low (when clearing the
interrupt request), the interrupt handler can allow execution of a floating-point
instruction, within the interrupt handler, before the error condition is cleared (by
FNCLEX, FNINIT, FNSAVE or FNSTENV). If execution of a non-control floating-point
instruction, within the floating-point interrupt handler, is not needed, the IGNNE# pin
can be tied high.
®
10.3.15 Intel

AT-Compatible Systems

The Intel
implementation of an AT-compatible numerics error reporting scheme. These features
DO NOT replace the external circuit. Logic is still required that decodes the OUT F0
instruction and latches the FERR# signal. The use of these features is described below.
• The NE bit in the Machine Status Register
• The IGNNE# pin
Note: The implementation of Intel
• The FERR# pin
The NE bit determines the action taken by the Intel
numerics error is detected. When set, this bit signals that non-DOS compatible error
handling is implemented. In this mode the Intel
software exception (16) if a numerics error is detected.
If the NE bit is reset, the Intel
an external circuit to control the time at which non-control numerics instructions are
allowed to execute. Note that floating-point control instructions such as FNINIT and
FNSAVE can be executed during a floating-point error condition regardless of the state
of IGNNE#.
10.4 Enhanced Bus Mode Operation for the Write-Back
Enhanced Intel
Note: The implementation of Intel
enhanced bus mode only (standard bus mode is not supported).
The Intel
However, when the internal cache is configured in write-back mode, the processor bus
operates in the Enhanced Bus mode. This section describes how the bus operation
changes for the Enhanced Bus mode when the internal cache is configured in write-
back mode.
10.4.1

Summary of Bus Differences

Differences between the Enhanced Bus and Standard Bus modes are summarized as:
1. Burst write capability is extended to four doubleword burst cycles (for write-back
cycles only).
®
Intel Quark SoC X1000 Core
Developer's Manual
226

Quark SoC X1000 Core Floating-Point Error Handling in

®
Quark SoC X1000 Core provides special features to allow the
provides the capability to control the IGNNE# pin via a register; the default
value of the register is 1'b0.
®
®
Quark SoC X1000 Core
®
Quark Core on Intel
®
Quark SoC X1000 Core operates in Standard Bus (write-through) mode.
®
Quark Core on Intel
®
Quark SoC X1000 Core when a
®
Quark SoC X1000 Core takes a
Quark SoC X1000 Core uses the IGNNE# pin to allow
®
Quark SoC X1000 supports
®
Intel Quark Core—Bus Operation
®

Quark SoC X1000

®
Quark SoC X1000
October 2013
Order Number: 329679-001US