Burst And Cache Line Fill Order; Slow Burst Cycle; Burst Order (Both Read And Write Bursts) - Intel Quark SoC X1000 Core Developer's Manual

Figure 93.

Slow Burst Cycle

CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
A3–A2
BE3#–BE0#
RDY#
BRDY#
KEN#
BLAST#
DATA
10.3.4.2

Burst and Cache Line Fill Order

The burst order used by the Intel
burst order is followed by any burst cycle (cache or not), cache line fill (burst or not) or
code prefetch.
The Intel
determined by the first address in the transfer. For example, if the first address was
104 the next three addresses in the burst will be 100, 10C and 108. An example of
burst address sequencing is shown in
Table 67.
®
Intel Quark SoC X1000 Core
Developer's Manual
206
Ti T1 T2
†
To Processor
®
Quark SoC X1000 Core presents each request for data in an order

Burst Order (Both Read and Write Bursts)

First Address
0
4
8
C
T2 T2 T2
†
†
®
Quark SoC X1000 Core is shown in
Figure 94.
Second Address Third Address
4 8
0 C
C 0
8 4
®
Intel Quark Core—Bus Operation
T2 T2 T2
†
†
242202-038
Table 67. This
Fourth Address
C
8
4
0
October 2013
Order Number: 329679-001US
T2