Page Cacheability (Pwt And Pcd Bits); Translation Lookaside Buffer; Page Cacheability; Page Level Protection Attributes - Intel Quark SoC X1000 Core Developer's Manual

Protected Mode Architecture—Intel
Table 34.

Page Level Protection Attributes

U/S
0
0
1
1
0
0
1
1
The R/W and U/S bits provide protection from user access on a page-by-page basis
because the bits are contained in the page table entry and the page directory table.
The U/S and R/W bits in the first-level page directory table apply to all entries in the
page table pointed to by that directory entry. The U/S and R/W bits in the second-level
page table entry apply only to the page described by that entry. The most restrictive
U/S and R/W bits from the page directory table and the page table entry are used to
address a page.
Example: If the U/S and R/W bits for the page directory entry were 10 (user
read/execute) and the U/S and R/W bits for the page table entry were 01 (no user
access at all), the access rights for the page would be 01, the numerically smaller of
the two.
Note: A given segment can be easily made read-only for level 0, 1, or 2 via use of segmented
protection mechanisms.
6.4.7

Page Cacheability (PWT and PCD Bits)

See Section 7.6, "Page Cacheability" on page 119
cacheability and the PWT and PCD bits.
6.4.8

Translation Lookaside Buffer

The Intel
paged virtual memory systems. However, performance would degrade substantially if
®
the Intel
memory reference. To solve this problem, the Intel
cache of the most recently accessed pages. This cache is called the Translation
Lookaside Buffer (TLB). The TLB is a four-way set associative 32-entry page table
cache. It automatically keeps the most commonly used page table entries in the Intel
Quark SoC X1000 Core. The 32-entry TLB coupled with a 4 Kbyte page size, results in
coverage of 128 Kbytes of memory addresses.
Figure 45
paging mechanism.
October 2013
Order Number: 329679-001US
®
Quark Core
R/W WP
0
1
0
1
0
1
0
1
®
Quark SoC X1000 Core paging hardware is designed to support demand
Quark SoC X1000 Core were required to access two levels of tables for every
illustrates how the TLB complements the Intel
User Access
0 None
0 None
0 Read/Execute
0 Read/Write/Execute
1 None
1 None
1 Read/Execute
1 Read/Write/Execute
for a detailed description of page
®
Quark SoC X1000 Core keeps a
Supervisor Access
Read/Write/Execute
Read/Write/Execute
Read/Write/Execute
Read/Write/Execute
Read/Execute
Read/Write/Execute
Read/Execute
Read/Write/Execute
®
Quark SoC X1000 Core's
®
Intel Quark SoC X1000 Core
Developer's Manual
®
103