Page Cacheability; Cacheability; On-Chip Cache Replacement Strategy; Encoding Of The Special Cycles For Write-Back Cache - Intel Quark SoC X1000 Core Developer's Manual

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On-Chip Cache—Intel Quark Core
The pseudo LRU mechanism works in the following manner: When a line must be
replaced, the cache first selects which of lines 11:10 and 13:12 was least recently
used. Then the cache determines which of the two lines was least recently used and
mark it for replacement. This decision tree is shown in
Table 38.

Encoding of the Special Cycles for Write-Back Cache

Write-Back
First Flush Ack Cycle
†
Flush
Second Flush Ack Cycle
Shutdown
HALT
Stop Grant Ack Cycle
† Write-Back Enhanced Intel
Figure 51.

On-Chip Cache Replacement Strategy

7.6

Page Cacheability

Two bits for cache control, PWT and PCD, are defined in the page table and page
directory entries. The states of these bits are driven out on the PWT and PCD pins
during memory access cycles.
The PWT bit controls the write policy for second-level caches used with the Intel
Quark SoC X1000 Core. Setting PWT=1 defines a write-through policy for the current
page while PWT=0 defines the possibility of write-back. The state of PWT is ignored
internally by the Intel
mode.
The PCD bit controls cacheability on a page-by-page basis. The PCD bit is internally
AND'ed with the KEN# signal to control cacheability on a cycle-by-cycle basis (see
Figure 52). PCD=0 enables caching while PCD=1 forbids it. Note that cache fills are
enabled when PCD=0 AND KEN#=0. This logical AND is implemented physically with a
NOR gate.
October 2013
Order Number: 329679-001US
Cycle Name
†
†
†
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Quark SoC X1000 Core only. FLUSH differs for Standard Mode.
All four lines
in the set valid?
Yes: I0 or I1
least recently used
B1 = 0?
Yes
Replace
I0
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Quark SoC X1000 Core for on-chip cache in write through
Figure
M/IO# D/C#
0 0
0 0
0 0
0 0
0 0
0 0
0 0
No
Replace
non-valid line
Yes
B0 = 0?
No: I2 or I3
least recently used
B2 = 0?
Yes
No
Replace Replace
I1 I2
51.
W/R# BE[3:0]# A[4:2]
1 0111
1 0111
1 1101
1 1101
1 1110
1 1011
1 1011
No
Replace
I3
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Intel Quark SoC X1000 Core
Developer's Manual
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