Control Register 1 (Cr1); Control Register 2 (Cr2); Control Register 3 (Cr3); Control Register 4 (Cr4) - Intel Quark SoC X1000 Core Developer's Manual

System Register Organization—Intel
Table 13. Interpreting Different Combinations of EM, TS and MP Bits (Sheet 2 of 2)
EM
1
1
1
Note: For Intel
the system software can save the floating-point status of the old task.
4.4.1.2

Control Register 1 (CR1)

CR1 is reserved for use in future Intel processors.
4.4.1.3

Control Register 2 (CR2)

CR2, shown in
that caused a page fault).
4.4.1.4

Control Register 3 (CR3)

CR3, shown in
structure hierarchy and two flags (PCD and PWT). Only the most-significant bits
(less the lower 12 bits) of the base address are specified; the lower 12 bits of the
address are assumed to be 0. The first paging structure must thus be aligned to a
page (4-KByte) boundary. The PCD and PWT flags control caching of that paging
structure in the processor's internal data caches (they do not control TLB caching of
page-directory information).
When using the physical address extension, the CR3 register contains the base
address of the page-directory-pointer table In IA-32e mode, the CR3 register
contains the base address of the PML4 table.
In the Intel
(PWT) (bit 3) and page cache disable (PCD) (bit 4). The page table entry (PTE) and
page directory entry (PDE) also contain PWT and PCD bits. PWT and PCD control
page cacheability. When a page is accessed in external memory, the states of PWT
and PCD are driven out on the PWT and PCD pins. The source of PWT and PCD can
be CR3, the PTE or the PDE. PWT and PCD are sourced from CR3 when the PDE is
being updated. When paging is disabled (PG = 0 in CR0), PCD and PWT are
assumed to be 0, regardless of their state in CR3.
A task switch through a task state segment (TSS) which changes the values in CR3,
or an explicit load into CR3 with any value, invalidates all cached page table entries
in the translation lookaside buffer (TLB).
The page directory base address in CR3 is a physical address. The page directory
can be paged out while its associated task is suspended, but the operating system
must ensure that the page directory is resident in physical memory before the task
is dispatched. The entry in the TSS for CR3 has a physical address, with no
provision for a present bit. This means that the page directory for a task must be
resident in physical memory. The CR3 image in a TSS must point to this area,
before the task can be dispatched through its TSS.
4.4.1.5

Control Register 4 (CR4)

CR4, shown in
extensions, and indicate operating system or executive support for specific processor
capabilities. The control registers can be read and loaded (or modified) using the move
to-or-from-control-registers forms of the MOV instruction. In protected mode, the MOV
October 2013
Order Number: 329679-001US
®
Quark Core
CR0 Bit
TS
0
1
1
®
Quark SoC X1000 Core, when MP=1 and TS=1, the processor generates a trap 7 so that
Figure 13, contains the page-fault linear address (the linear address
Figure 13, contains the physical address of the base of the paging-
®
Quark SoC X1000 Core, CR3 contains two bits, page write-through
Figure 14, contains a group of flags that enable several architectural
Instruction Type
MP Floating-Point
1 Exception 7
0 Exception 7
1 Exception 7
Intel
Wait
Execute
Execute
Exception 7
®
Quark SoC X1000 Core
Developer's Manual
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