32-Bit Extensions Of The Instruction Set; Fields Within Intel ® Quark Core Instructions - Intel Quark SoC X1000 Core Developer's Manual

Table 75. Fields within Intel
Field
Name
w
d
s
reg
mod
r/m
ss
index
base
sreg2
sreg3
tttn
Note: Table 89
12.2.2

32-Bit Extensions of the Instruction Set

With the Intel
orthogonal directions: 32-bit forms of all 16-bit instructions support the 32-bit data
types and 32-bit addressing modes are available for all instructions referencing
memory. This orthogonal instruction set extension is accomplished having a Default (D)
bit in the code segment descriptor, and by having two prefixes to the instruction set.
Whether the instruction defaults to operations of 16 bits or 32 bits depends on the
setting of the D bit in the code segment descriptor, which gives the default length
(either 32 bits or 16 bits) for both operands and effective addresses when executing
that code segment. In Real Address Mode or Virtual 8086 Mode, no code segment
descriptors are used, but the Intel
when operating in those modes (for 16-bit default sizes).
Two prefixes, the Operand Size Prefix and the Effective Address Size Prefix, allow
overriding individually the Default selection of operand size and effective address size.
These prefixes may precede any opcode bytes and affect only the instruction they
precede. If necessary, one or both of the prefixes may be placed before the opcode
bytes. The Operand Size Prefix and the Effective Address Prefix toggle the operand size
or the effective address size, respectively, to the value "opposite" the Default setting.
For example, when the default operand size is for 32-bit data operations, the presence
of the Operand Size Prefix toggles the instruction to 16-bit data operation. When the
default effective address size is 16 bits, the presence of the Effective Address Size
prefix toggles the instruction to use 32-bit effective address computations.
These 32-bit extensions are available in all Intel
including Real Address Mode or Virtual 8086 Mode. In these modes the default is
always 16 bits, so prefixes are needed to specify 32-bit operands or addresses. For
instructions with more than one prefix, the order of prefixes is unimportant.
Unless specified otherwise, instructions with 8-bit and 16-bit operands do not affect the
contents of the high-order bits of the extended registers.
®
Intel Quark SoC X1000 Core
Developer's Manual
254
®
Quark Core Instructions
Specifies whether data is byte or full size (full size is either 16 or 32 bits)
Specifies direction of data operation
Specifies whether an immediate data field must be sign-extended
General register specifier
Address mode specifier (effective address can be a general register)
Scale factor for scaled index address mode
General register to be used as index register
General register to be used as base register
Segment register specifier for CS, SS, DS, ES
Segment register specifier for CS, SS, DS, ES, FS, GS
For conditional instructions, specifies a condition asserted or a condition negated
through Table 93 show encoding of individual instructions.
®
Quark SoC X1000 Core, the instruction set is extended in two
®
Intel Quark Core—Instruction Set Summary
Description
®
Quark SoC X1000 Core assumes a D value of 0
®
Quark SoC X1000 Core modes,
Number of
Bits
1
1
1
3
2 for mod;
3 for r/m
2
3
3
2
3
4
October 2013
Order Number: 329679-001US