Inserting Wait States; Basic 2-2 Bus Cycle - Intel Quark SoC X1000 Core Developer's Manual

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Bus Operation—Intel Quark Core
Figure 86.

Basic 2-2 Bus Cycle

CLK
ADS#
A31–A2
M/IO#
D/C#
BE3#–BE0#
W/R#
RDY#
BLAST#
DATA
PCHK#
The non-burst ready input (RDY#) is asserted by the external system in the second
clock. RDY# indicates that the external system has presented valid data on the data
pins in response to a read or the external system has accepted data in response to a
write.
The Intel
cycle is complete if RDY# is asserted (LOW) when sampled. Note that RDY# is ignored
at the end of the first clock of the bus cycle.
The burst last signal (BLAST#) is asserted (LOW) by the Intel
during the second clock of the first cycle in all bus transfers illustrated in
This indicates that each transfer is complete after a single cycle. The Intel
X1000 Core asserts BLAST# in the last cycle, "T2", of a bus transfer.
The timing of the parity check output (PCHK#) is shown in
SoC X1000 Core drives the PCHK# output one clock after RDY# or BRDY# terminates a
read cycle. PCHK# indicates the parity status for the data sampled at the end of the
previous clock. The PCHK# signal can be used by the external system. The Intel
Quark SoC X1000 Core does nothing in response to the PCHK# output.
10.3.1.2

Inserting Wait States

The external system can insert wait states into the basic 2-2 cycle by deasserting RDY#
at the end of the second clock. RDY# must be deasserted to insert a wait state.
Figure 87
added. Any number of wait states can be added to an Intel
bus cycle by maintaining RDY# deasserted.
October 2013
Order Number: 329679-001US
Ti T1 T2
Read
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To Processor
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From Processor
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Quark SoC X1000 Core samples RDY# at the end of the second clock. The
illustrates a simple non-burst, non-cacheable signal with one wait state
T1 T2 T1
‡
†
Write Read
Figure
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T2 T1 T2 Ti
†
‡
Write
242202-031
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Quark SoC X1000 Core
Figure 86.
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Quark SoC
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86. The Intel Quark
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Quark SoC X1000 Core
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Intel Quark SoC X1000 Core
Developer's Manual
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