Pin State During Reset - Intel Quark SoC X1000 Core Developer's Manual

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Hardware Interface—Intel
Table 56.
9.5.2

Pin State During Reset

The Intel
BOFF# requests regardless of the state of RESET. Thus, even though the processor is in
reset, it can float its bus in response to any of these requests.
While in reset, the Intel
if the HOLD, AHOLD and BOFF# requests are inactive. Note that the address (A[31:2],
BE[3:0]#) and cycle definition (M/IO#, D/C#, W/R#) pins are undefined from the time
reset is asserted until the start of the first bus cycle. All undefined pins (except FERR#)
assume known values at the beginning of the first bus cycle. The first bus cycle is
always a code fetch to address FFFFFFF0H.
October 2013
Order Number: 329679-001US
Quark Core
Floating-Point Values after Reset
FEA 00000000h
FCS 0000h
FDS 0000h
FOP 000h
FSTACK Undefined
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Quark SoC X1000 Core recognizes and can respond to HOLD, AHOLD, and
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Quark SoC X1000 Core bus is in the state shown in
(Sheet 2 of 2)
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
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Intel Quark SoC X1000 Core
Developer's Manual
Figure 72
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