Quark Soc X1000 Core; Access Rights - Intel Quark SoC X1000 Core Developer's Manual

6.4.4 #GP Faults for Intel
Failures to load the PDPTE registers with PAE paging causes #GP fault.
• If any of the PDPTEs sets both the P flag (bit 0) and any reserved bit, it causes a
general-protection exception (#GP(0)) and the PDPTEs are not loaded.
• If any of the PDPTE entries have P flag (bit 0) cleared and any of the reserved bits
are set this does not cause #GP(0) fault.
#GP(0) Fault is caused when reading/writing to IA32_EFER, IA32_MISC_ENABLES
MSRs:
• In privilege level greater than 0
• In virtual-8086 mode
• Unimplemented MSRs
• Writing to reserved bits
6.4.5

Access Rights

There is a translation for a linear address if the processes described in
completes and produces a physical address. Whether an access is permitted by a
translation is determined by the access rights specified by the paging-structure entries
controlling the translation; paging-mode modifiers in CR0, CR4, and the IA32_EFER
MSR; and the mode of the access.
Note: With PAE paging, the PDPTEs do not determine access rights.
Every access to a linear address is either a supervisor-mode access or a usermode
access. All accesses performed while the current privilege level (CPL) is less than 3 are
supervisor-mode accesses. If CPL = 3, accesses are generally user-mode accesses.
However, some operations implicitly access system data structures with linear
addresses; the resulting accesses to those data structures are supervisormode
accesses regardless of CPL. Examples of such implicit supervisor accesses include the
following: accesses to the global descriptor table (GDT) or local descriptor table (LDT)
to load a segment descriptor; accesses to the interrupt descriptor table (IDT) when
delivering an interrupt or exception; and accesses to the task-state segment (TSS) as
part of a task switch or change of CPL.
The following items detail how paging determines access rights:
For supervisor-mode accesses:
• Data reads.
Data may be read from any linear address with a valid translation.
• Data writes.
— If CR0.WP = 0, data may be written to any linear address with a valid
translation.
— If CR0.WP = 1, data may be written to any linear address with a valid
translation for which the R/W flag (bit 1) is 1 in every paging-structure entry
controlling the translation.
• Instruction fetches.
— For 32-bit paging or if IA32_EFER.NXE = 0, access rights depend on the value
of CR4.SMEP:
If CR4.SMEP = 0, instructions may be fetched from any linear address with a
valid translation.
®
Intel

Quark SoC X1000 Core

Developer's Manual
100
®
Intel
®
Quark SoC X1000 Core
Quark Core—Protected Mode Architecture
Section 6.4.3.2
Order Number: 329679-001US
October 2013