Effect Of Changing Ken# During A Cache Line Fill; Burst Cacheable Cycle - Intel Quark SoC X1000 Core Developer's Manual

Figure 91.

Burst Cacheable Cycle

CLK
ADS#
A31–A4
M/IO#
D/C#
W/R#
A3–A2
BE3#–BE0#
RDY#
BRDY#
KEN#
BLAST#
DATA
PCHK#
10.3.3.4

Effect of Changing KEN# during a Cache Line Fill

KEN# can change multiple times as long as it arrives at its final value in the clock
before RDY# or BRDY# is asserted. This is illustrated in
of BLAST# follows that of KEN# by one clock. The Intel
samples KEN# every clock and uses the value returned in the clock before BRDY# or
RDY# to determine if a bus cycle would be a cache line fill. Similarly, it uses the value
of KEN# in the last cycle before early RDY# to load the line just retrieved from memory
into the cache. KEN# is sampled every clock and it must satisfy setup and hold times.
KEN# can also change multiple times before a burst cycle, as long as it arrives at its
final value one clock before BRDY# or RDY# is asserted.
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Intel Quark SoC X1000 Core
Developer's Manual
204
Ti T1
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To Processor
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Intel
T2 T2 T2
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†
Figure 92. Note that the timing
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Quark SoC X1000 Core
Quark Core—Bus Operation
T2 Ti
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242202-036
October 2013
Order Number: 329679-001US