Cache Testability Write - Intel Quark SoC X1000 Core Developer's Manual

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Testability—Intel Quark Core
Cache Data Test Register: TR3
The cache fill buffer and the cache read buffer can only be accessed through TR3. Data
to be written to the cache fill buffer must first be written to TR3. Data read from the
cache read buffer must be loaded into TR3.
TR3 is 32 bits wide while the cache fill and read buffers are 128 bits wide. 32 bits of
data must be written to TR3 four times to fill the cache fill buffer. 32 bits of data must
be read from TR3 four times to empty the cache read buffer. The entry select bits in
TR5 determine which 32 bits of data TR3 will access in the buffers.
Cache Status Test Register: TR4
TR4 handles tag, LRU and valid bit information during cache tests. TR4 must be loaded
with a tag and a valid bit before a write to the cache. After a read from a cache entry,
TR4 contains the tag and valid bit from that entry, and the LRU bits and four valid bits
from the accessed set.
Cache Control Test Register: TR5
TR5 specifies the testability operation to be performed and the set and entry to be
accessed. The set select field determines the set to be accessed. Note that the Intel
Quark SoC X1000 Core has an 8-bit set select field and 256 sets.
The function of the two entry select bits depends on the state of the control bits. When
the fill or read buffers are being accessed, the entry select bits point to the 32-bit
location in the buffer being accessed. When a cache location is specified, the entry
select bits point to one of the four entries in a set (refer to
Five testability functions can be performed on the cache. The two control bits in TR5
specify the operation to be executed. The five operations are:
1. Write cache fill buffer
2. Perform a cache testability write
3. Perform a cache testability read
4. Read the cache read buffer
5. Perform a cache flush
Table 96
functions.
control operation.
The cache tests attempt to use as much of the normal operating circuitry as possible.
Therefore, when cache tests are being performed, the cache must be disabled (i.e.,the
CD and NW bits in control register 0 (CR0) must be set to 1 to disable the cache). See
Chapter 7.0, "On-Chip Cache."
B.1.2

Cache Testability Write

A testability write to the cache is a two step process. First the cache fill buffer must be
loaded with 128 bits of data and TR4 loaded with the tag and valid bit. Next the
contents of the fill buffer are written to a cache location.
Loading the fill buffer is accomplished by first writing to the entry select bits in TR5 and
setting the control bits in TR5 to 00. The entry select bits identify one of four 32-bit
locations in the cache fill buffer to put 32 bits of data. Following the write to TR5, TR3 is
written with 32 bits of data which are immediately placed in the cache fill buffer. Writing
October 2013
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shows the encoding of the two control bits in TR5 for the cache testability
Table 96 also shows the functionality of the entry and set select bits for each
for more information.
Table 96).
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Intel Quark SoC X1000 Core
Developer's Manual
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