Memory And I/O Space Organization; Physical Memory And I/O Spaces; Generating A[31:0] From Be[3:0]# And A[31:A2] - Intel Quark SoC X1000 Core Developer's Manual

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Bus Operation—Intel Quark Core
Table 61.

Generating A[31:0] from BE[3:0]# and A[31:A2]

A31
A31
A31
A31
A31
Figure 77.

Physical Memory and I/O Spaces

10.1.1.1

Memory and I/O Space Organization

The Intel
can be 8, 16, or 32 bits wide. The byte enable signals, BE[3:0]#, allow byte granularity
when addressing any memory or I/O structure, whether 8, 16, or 32 bits wide.
The Intel
allow direct connection to 16- and 8-bit memories and I/O devices. Cycles of 32-, 16-
and 8-bits may occur in any sequence, since the BS8# and BS16# signals are sampled
during each bus cycle.
Memory and I/O spaces that are 32-bit wide are organized as arrays of four bytes each.
Each four bytes consists of four individually addressable bytes at consecutive byte
addresses (see
D[7:0]; the highest-addressed byte with D[31:24]. Each 4 bytes begin at an address
that is divisible by four.
October 2013
Order Number: 329679-001US
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Intel Quark SoC X1000 Core Address Signals
Physical Address
... A2 A1
... A2 0
... A2 0
... A2 1
... A2 1
FFFFFFFFH
Physical
Memory
4 Gbyte
00000000H
Physical Memory
Space
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Quark SoC X1000 Core datapath to memory and input/output (I/O) spaces
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Quark SoC X1000 Core includes bus control pins, BS16# and BS8#, which
Figure 78). The lowest addressed byte is associated with data signals
BE3# BE2#
A0
0 X X
1 X X
0 X 0
1 0 1
Not
Accessible
Not
Accessible
0000FFFFH
64 Kbyte
00000000H
I/O Space
BE1# BE0#
X 0
0 1
1 1
1 1
Accessible
Programmed
I/O Space
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Intel Quark SoC X1000 Core
Developer's Manual
185