Logic To Generate A1, Bhe# And Ble# For 16-Bit Buses - Intel Quark SoC X1000 Core Developer's Manual

Figure 81.

Logic to Generate A1, BHE# and BLE# for 16-Bit Buses

Combinations of BE[3:0]# that never occur are those in which two or three asserted
byte enables are separated by one or more deasserted byte enables. These
combinations are "don't care" conditions in the decoder. A decoder can use the non-
occurring BE[3:0]# combinations to its best advantage.
Figure 82
wide memories. External byte swapping logic is needed on the data lines so that data is
supplied to and received from the Intel
pins (see
®
Intel Quark SoC X1000 Core
Developer's Manual
190
®
shows a Intel Quark SoC X1000 Core data bus interface to 16- and 8-bit
Table 63).
®
Intel
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Quark SoC X1000 Core on the correct data
Quark Core—Bus Operation
October 2013
Order Number: 329679-001US