Bus Hold Acknowledge Output (Hlda); Backoff Input (Boff#); Cache Invalidation - Intel Quark SoC X1000 Core Developer's Manual

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Hardware Interface—Intel
performing a code fetch, and that cycle is backed off (BOFF#), the Intel
X1000 Core will recognize HOLD before restarting the cycle. The code fetch can be non-
cacheable or cacheable and non-burst or burst. The BREQ, HLDA, PCHK# and FERR#
pins are not floated during bus hold. The Intel
bus in this state until the HOLD is de-asserted. Refer to
diagrams for bus hold cycles and HOLD request acknowledge during BOFF#.
The Intel
not provided for the outputs that are floated in response to HOLD. HOLD is active high
and is not provided with an internal pull-down resistor. HOLD must satisfy setup and
hold times t
9.2.9.3

Bus Hold Acknowledge Output (HLDA)

HLDA indicates that the Intel
local bus master. HLDA goes active in response to a hold request presented on the
HOLD pin. HLDA is driven active in the same clock in which the Intel
X1000 Core floats its bus.
HLDA is driven inactive when leaving bus hold, and the Intel
resumes driving the bus. The Intel
activity during bus hold because the internal cache satisfies the majority of bus
requests. HLDA is active high and remains driven during bus hold.
9.2.9.4

Backoff Input (BOFF#)

Asserting the BOFF# input forces the Intel
of its bus in the next clock. The pins floated are exactly the same as those floated in
response to HOLD. The response to BOFF# differs from the response to HOLD in two
ways: First, the bus is floated immediately in response to BOFF#, whereas the Intel
Quark SoC X1000 Core completes the current bus cycle before floating its bus in
response to HOLD. Second the Intel
response to BOFF#.
The Intel
negation, the Intel
when BOFF# was asserted. To the internal execution engine the effect of BOFF# is the
same as inserting a few wait states to the original cycle. Refer to
description of bus cycle restart.
Any data returned to the Intel
ignored. BOFF# has higher priority than RDY# or BRDY#. If both BOFF# and ready are
returned in the same clock, BOFF# takes effect. If BOFF# is asserted while the bus is
idle, the Intel
low and must meet setup and hold times t
9.2.10

Cache Invalidation

The AHOLD and EADS# inputs are used during cache invalidation cycles. AHOLD
conditions the Intel
address input. EADS# indicates that an external address is actually valid on the
address inputs. Activating EADS# causes the Intel
external address bus and perform an internal cache invalidation cycle to the address
indicated. Refer to
October 2013
Order Number: 329679-001US
Quark Core
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Quark SoC X1000 Core recognizes HOLD during reset. Pull-up resistors are
and t for proper chip operation.
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Quark SoC X1000 Core has given the bus to another
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Quark SoC X1000 Core remains in bus hold until BOFF# is negated. Upon
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Quark SoC X1000 Core restarts the bus cycle that was aborted
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Quark SoC X1000 Core floats its bus in the next clock. BOFF# is active
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Quark SoC X1000 Core address lines, A[31:4], to accept an
Section 10.3.8
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Quark SoC X1000 Core maintains its
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Quark SoC X1000 Core does not cease internal
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Quark SoC X1000 Core to release control
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Quark SoC X1000 Core does not assert HLDA in
Quark SoC X1000 Core while BOFF# is asserted is
and t for proper chip operation.
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Quark SoC X1000 Core to read the
for cache invalidation cycle timing.
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Quark SoC
Section 10.3.9 for timing
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Quark SoC
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Quark SoC X1000 Core
Section 10.3.12
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Intel Quark SoC X1000 Core
Developer's Manual
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for a
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