Encoding Of Address Mode; 3-Bit Sreg3 Field - Intel Quark SoC X1000 Core Developer's Manual

Instruction Set Summary—Intel
Table 80.
12.2.3.4

Encoding of Address Mode

Except for special instructions, such as PUSH or POP, where the addressing mode is
pre-determined, the addressing mode for the current instruction is specified by
addressing bytes following the primary opcode. The primary addressing byte is the
"mod r/m" byte, and a second byte of addressing information, the "s-i-b" (scale-index-
base) byte, can be specified.
The s-i-b (scale-index-base byte) byte is specified when using 32-bit addressing mode
and the "mod r/m" byte has r/m = 100 and mod = 00, 01 or 10. When the sib byte is
present, the 32-bit addressing mode is a function of the mod, ss, index, and base
fields.
The primary addressing byte, the "mod r/m" byte, also contains three bits (shown as
TTT in Figure
bits, however, may also be used as a register field (reg).
When calculating an effective address, either 16-bit addressing or 32-bit addressing is
used. 16-bit addressing uses 16-bit address components to calculate the effective
address, and 32-bit addressing uses 32-bit address components to calculate the
effective address. When 16-bit addressing is used, the "mod r/m" byte is interpreted as
a 16-bit addressing mode specifier. When 32-bit addressing is used, the "mod r/m"
byte is interpreted as a 32-bit addressing mode specifier.
The following tables define encodings of all 16-bit and 32-bit addressing modes.
October 2013
Order Number: 329679-001US
®
Quark Core

3-Bit sreg3 Field

3-bit sreg3 Field
000
001
010
011
100
101
110
111
128) sometimes used as an extension of the primary opcode. The three
Segment Register Selected
ES
CS
SS
DS
FS
GS
do not use
do not use
®
Intel Quark SoC X1000 Core
Developer's Manual
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