Processor Reset Requirements; Figure 31. Reset#/Reset2# Routing Guidelines; Table 15. Reset#/Reset2# Routing Guidelines (See Figure 31) - Intel 815EG Design Manual

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Processor Reset Requirements

Universal PGA370 designs must route the AGTL/AGTL+ reset signal from the chipset to two pins
on the processor as well as to the debug port connector. This reset signal is connected to the
following pins at the PGA370 socket:
• AH4 (RESET#). The reset signal is connected to this pin for the Pentium III processor
(CPUID=068xh), Celeron processor (CPUID=068xh), and future 0.13 micron socket 370
processors
• X4 (Reset2# or GND, depending on processor). The X4 pin is RESET2# for Pentium III
processor (CPUID=068xh) and Celeron processor (CPUID=068xh). X4 is GND for future
0.13 micron socket 370 processors. An additional 1 kΩ resistor is connected in series with pin
X4 to the reset circuitry since pin X4 is a ground pin in future 0.13 micron socket 370
processors.
The AGTL/AGTL+ reset signal must always terminate to VTT on the motherboard.
Designs that do not support the debug port will not utilize the 240 Ω series resistor or the
connection of RESET# to the debug port connector. RESET2# is not required for platforms that
do not support the Celeron processor (CPUID=068xh). Pin X4 should then be connected to
ground.
The routing rules for the AGTL/AGTL+ reset signal are shown in Figure 31.

Figure 31. RESET#/RESET2# Routing Guidelines

Table 15. RESET#/RESET2# Routing Guidelines (see Figure 31)

Parameter
LenCS
LenITP
LenCPU
cs_rtt_stub
cpu_rtt_stub
®
Intel 815EG Chipset Platform Design Guide
VTT
91 Ω
cs_rtt_stub
Chipset
lenCS
Minimum (in)
0.5
1
0.5
0.5
0.5
System Bus Design Guidelines
lenITP
VTT
86 Ω
240 Ω
cpu_rtt_stub
lenCPU
22 Ω
10 pF
Maximum (in)
1.5
3
1.5
1.5
1.5
ITP
Daisy chain
1 kΩ
Pin X4
Processor
Pin AH4
sys_bus_reset_routin
65