Smram; Smi# Timing For Servicing An I/O Trap - Intel Quark SoC X1000 Core Developer's Manual

The number of CLKs required to complete the SMM state save and restore is dependent
on-system memory performance. The values listed in
memory writes (two CLK cycles), 2-1-1-1 burst read cycles, and zero wait-state non-
burst reads (2 CLK cycles). Additionally, it is assumed that the data read during the
SMM state restore sequence is not cacheable.
Figure 55.

SMI# Timing for Servicing an I/O Trap

CLK
SMI#
BRDY#
Note: Setup time (A) for recognition on I/O instruction boundary.
Figure 56
®
Figure 56. Intel Quark SoC X1000 Core SMIACT# Timing
CLK
SMI#
ADS#
BRDY#
SMIACT#
8.3.3

SMRAM

The Intel
restore operations during an SMI# and RSM. The SMI# handler, which also resides in
SMRAM, uses the SMRAM space to store code, data and stacks. In addition, the SMI#
handler can use the SMRAM for system management information such as the system
configuration, configuration of a powered-down device, and system design-specific
information.
®
Intel Quark SoC X1000 Core
Developer's Manual
130
Intel
SMI#
Sampled
t t
su nd
can be used for latency calculations.
T1 T2
A
Normal State
®
Quark SoC X1000 Core uses the SMRAM space for state save and state
®
Quark Core—System Management Mode (SMM) Architectures
Table 42
A
B
C D E
State SIMM State
Save Handler Restore
System Management Mode
assume zero wait-state
A5232-01
G
F
Normal
State
Normal State
A5233-01
October 2013
Order Number: 329679-001US