Debugging Support; Breakpoint Instruction; Single-Step Trap; Debug Registers - Intel Quark SoC X1000 Core Developer's Manual

11.0

Debugging Support

The Intel
debugging process. The three categories of on-chip debugging aids are:
1. Code execution breakpoint opcode (0CCH)
2. Single-step capability provided by the TF bit in the Flag register
3. Code and data breakpoint capability provided by the Debug Registers DR[3:0],
DR6, and DR7
11.1

Breakpoint Instruction

A single-byte opcode breakpoint instruction is available for use by software debuggers.
The breakpoint opcode, 0CCH, generates an exception 3 trap when executed. In typical
use, a debugger program "plants" the breakpoint instruction at all desired code
execution breakpoints. The single-byte breakpoint opcode is an alias for the two-byte
general software interrupt instruction INT n, where n=3. The only difference between
INT 3 (0CCh) and INT n is that INT 3 is never IOPL-sensitive, whereas INT n is IOPL-
sensitive in Protected Mode and Virtual 8086 Mode.
11.2

Single-Step Trap

When the single-step flag (TF, bit 8) in the EFLAG register is set at the end of an
instruction, a single-step exception occurs. The single-step exception is auto vectored
to exception number 1. Precisely, exception 1 occurs as a trap after the instruction
following the instruction that set TF. In typical practice, a debugger sets the TF bit of a
flag register image on the debugger's stack. Typically, it then transfers control to the
user program and loads the flag image with a signal instruction, the IRET instruction.
The single-step trap occurs after executing one instruction of the user program.
Because exception 1 occurs as a trap (that is, it occurs after the instruction has
executed), the CS:EIP pushed onto the debugger's stack points to the next unexecuted
instruction of the program being debugged. Therefore, by ending with an IRET
instruction, an exception 1 handler can efficiently support single-stepping through a
user program.
11.3

Debug Registers

The Debug Registers are an advanced debugging feature of the Intel
X1000 Core. They allow data access breakpoints and code execution breakpoints.
Because the breakpoints are indicated by on-chip registers, an instruction execution
breakpoint can be placed in ROM code or in code shared by several tasks, neither of
which can be supported by the INT3 breakpoint opcode.
The Intel
specify up to four distinct breakpoint addresses, breakpoint control options, and read
breakpoint status. Initially after reset, breakpoints are in the disabled state. Therefore,
no breakpoints occur unless the debug registers are programmed. Breakpoints set up
in the Debug Registers are auto-vectored to exception number 1.
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Intel Quark SoC X1000 Core
Developer's Manual
246
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Quark SoC X1000 Core provides several features that simplify the
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Quark SoC X1000 Core contains six Debug Registers, providing the ability to
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Intel Quark Core—Debugging Support
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Quark SoC
Order Number: 329679-001US
October 2013