Rdmsr; Rdtsc; Wrmsr - Intel Quark SoC X1000 Core Developer's Manual

In 64-bit mode, default operation size is 64 bits. Use of the REX.W prefix promotes
operation to 128 bits. Note that CMPXCHG16B requires that the destination (memory)
operand be 16-byte aligned.
12.2.5.2

RDMSR

Description
Reads the contents of a 64-bit model specific register (MSR) specified in the ECX
register into registers EDX:EAX. (On processors that support the Intel 64 architecture,
the high-order 32 bits of RCX are ignored.) The EDX register is loaded with the high-
order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. (On
processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX
and RDX are cleared.) If fewer than 64 bits are implemented in the MSR being read,
the values returned to EDX:EAX in unimplemented bit locations are undefined.
This instruction must be executed at privilege level 0 or in real-address mode;
otherwise, a general protection exception #GP(0) will be generated. Specifying a
reserved or unimplemented MSR address in ECX will also cause a general protection
exception.
The MSRs control functions for testability, execution tracing, performance-monitoring,
and machine check errors. Note that each processor family has its own set of MSRs.
The CPUID instruction should be used to determine whether MSRs are supported
(CPUID.01H:EDX[5] = 1) before using this instruction.
12.2.5.3

RDTSC

Description
Loads the current value of the processor's time-stamp counter (a 64-bit MSR) into the
EDX:EAX registers. The EDX register is loaded with the high-order 32 bits of the MSR
and the EAX register is loaded with the low-order 32 bits. (On processors that support
the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.)
The processor monotonically increments the time-stamp counter MSR every clock cycle
and resets it to 0 whenever the processor is reset.
When in protected or virtual 8086 mode, the time stamp disable (TSD) flag in register
CR4 restricts the use of the RDTSC instruction as follows. When the TSD flag is clear,
the RDTSC instruction can be executed at any privilege level; when the flag is set, the
instruction can only be executed at privilege level 0. (When in real-address mode, the
RDTSC instruction is always enabled.)
The time-stamp counter can also be read with the RDMSR instruction, when executing
at privilege level 0.
12.2.5.4

WRMSR

Description
Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR)
specified in the ECX register. The contents of the EDX register are copied to high-order
32 bits of the selected MSR and the contents of the EAX register are copied to low-
order 32 bits of the MSR. Undefined or reserved bits in an MSR should be set to values
previously read.
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Intel Quark SoC X1000 Core
Developer's Manual
264
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Intel Quark Core—Instruction Set Summary
Order Number: 329679-001US
October 2013