Bus Hold; Cache Invalidation Cycle Concurrent With Line Fill - Intel Quark SoC X1000 Core Developer's Manual

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Bus Operation—Intel Quark Core
Figure 104. Cache Invalidation Cycle Concurrent with Line Fill
CLK
ADS#
ADDR
AHOLD
EADS#
RDY#
BRDY#
KEN#
DATA
NOTES:
1. Data returned must be consistent if its address equals the invalidation address in this clock.
2. Data returned is not cached if its address equals the invalidation address in this clock.
10.3.9

Bus Hold

The Intel
using the bus hold request (HOLD) and bus hold acknowledge (HLDA) pins. Asserting
the HOLD input indicates that another bus master has requested control of the Intel
Quark SoC X1000 Core bus. The Intel
bus and asserting HLDA when the current bus cycle, or sequence of locked cycles, is
complete. An example of a HOLD/HLDA transaction is shown in
Quark SoC X1000 Core can respond to HOLD by floating its bus and asserting HLDA
while RESET is asserted.
October 2013
Order Number: 329679-001US
Ti T1 T2
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To Processor
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Quark SoC X1000 Core provides a bus hold, hold acknowledge protocol
T2 T2 T2
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1 2
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Quark SoC X1000 Core responds by floating its
T2 T2 Ti
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242202-093
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Figure 105. The Intel
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Intel Quark SoC X1000 Core
Developer's Manual
217
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