Intel Quark SoC X1000 Core Developer's Manual page 277

Instruction Set Summary—Intel
Table 89. Clock Count Summary (Sheet 11 of 13)
Instruction
INVD = Invalidate Data
Cache
WBINVD = Write-Back and
Invalidate Data Cache
INVLPG = Invalidate TLB Entry
INVLPG memory
PREFIX BYTES
Address Size Prefix
LOCK = Bus Lock Prefix
Operand Size Prefix
Segment Override Prefix
CS:
DS:
ES:
FS:
GS:
SS:
PROTECTION CONTROL
ARPL = Adjust Requested Privilege Level
From register
From memory
LAR = Load Access Rights
From register
From memory
LGDT = Load Global Descriptor
Table register
LIDT = Load Interrupt Descriptor
Table register
LLDT = Load Local Descriptor
Table register from reg.
Table register from mem.
LMSW = Load Machine Status Word
From register
From memory
LSL = Load Segment Limit
From register
From memory
Note: See
October 2013
Order Number: 329679-001US
®
Quark Core
0000 1111 : 0000 1000
0000 1111 : 0000 1001
0000 1111 : 0000 0001 : mod 111 r/m
0110 0111
1111 0000
0110 0110
0010 1110
0011 1110
0010 0110
0110 0100
0110 0101
0011 0110
0110 0011 : 11 reg1 reg2
0110 0011 : mod reg r/m
0000 1111 : 0000 0010 : 11 reg1 reg2
0000 1111 : 0000 0010 : mod reg r/m
0000 1111 : 0000 0001 : mod 010 r/m
0000 1111 : 0000 0001 : mod 011 r/m
0000 1111 : 0000 0000 : 11 010 reg
0000 1111 : 0000 0000 : mod 010 r/m
0000 1111 : 0000 0001 : 11 110 reg
0000 1111 : 0000 0001 : mod 110 r/m
0000 1111 : 0000 0011 : 11 reg1 reg2
0000 1111 : 0000 0011 : mod reg r/m
Table 92 for notes and abbreviations for items in this table.
Cache
Format
12/11
Penalty
if
Notes
Hit Cache
Miss
4
5
H/NH
1
1
1
1
1
1
1
1
1
9
9
11 3
11 5
12 5
12 5
11 3
11 6
13
13 1
10 3
10 6
®
Intel Quark SoC X1000 Core
Developer's Manual
277