About This Manual; Manual Contents - Intel Quark SoC X1000 Core Developer's Manual

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About this Manual—Intel
1.0

About this Manual

This manual describes the embedded Intel
use by hardware designers familiar with the principles of embedded microprocessors
and with the Intel
1.1

Manual Contents

Table 1 summarizes the contents of the remaining chapters and appendixes. The
remainder of this chapter describes notation conventions and special terminology used
throughout the manual and provides references to related documentation.
Table 1. Manual Contents (Sheet 1 of 2)
Chapter
Chapter 2.0, "Intel
Quark SoC X1000 Core
Overview"
Chapter 3.0,
"Architectural Overview"
Chapter 4.0, "System
Register Organization"
Chapter 5.0, "Real Mode
Architecture"
Chapter 6.0, "Protected
Mode Architecture"
Chapter 7.0, "On-Chip
Cache"
Chapter 8.0, "System
Management Mode
(SMM) Architectures"
Chapter 9.0, "Hardware
Interface"
Chapter 10.0, "Bus
Operation"
Chapter 11.0,
"Debugging Support"
Chapter 12.0,
"Instruction Set
Summary"
October 2013
Order Number: 329679-001US
Quark Core
®
Quark SoC X1000 Core architecture.
Provides an overview of the current embedded Intel
®
including product features, system components, system architecture, and
applications. This chapter also lists product frequency, voltage, and package
offerings.
Describes the Intel
overview of the processor's functional units.
Details the Intel
architecture registers, system-level registers, debug and test registers, and Intel
Quark SoC X1000 Core Model Specific Registers (MSRs).
When the Intel
Mode, which is described in this chapter.
Describes Protected Mode, including segmentation, protection, and paging.
®
The Intel Quark SoC X1000 Core contains an on-chip cache, also known as L1
cache. This chapter describes its functionality.
Describes the System Management Mode architecture of the Intel
X1000 Core, including System Management Mode interrupt processing and
programming.
Describes the hardware interface of the Intel
signal descriptions, interrupt interfaces, write buffers, reset and initialization, and
clock control.
Describes the features of the processor bus, including bus cycle handling,
interrupt and reset signals, cache control, and floating-point error control.
Describes the Intel
breakpoint instruction, single-step trap, and debug registers.
Describes the Intel
each field within the instructions.
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Quark SoC X1000 Core. It is intended for
Description
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Quark SoC X1000 Core internal architecture, with an
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Quark SoC X1000 Core register set, including the base
®
Quark SoC X1000 Core is powered-up, it is initialized in Real
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Quark SoC X1000 Core debugging support, including the
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Quark SoC X1000 Core instruction set and the encoding of
®
Quark SoC X1000 Core,
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Quark SoC
®
Quark SoC X1000 Core, including
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Intel Quark SoC X1000 Core
Developer's Manual
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