System With Second-Level Cache - Intel Quark SoC X1000 Core Developer's Manual

Figure 103. System with Second-Level Cache
If the system asserts EADS# before the first data in the line fill is returned to the Intel
Quark SoC X1000 Core, the system must return data consistent with the new data in
the external memory upon resumption of the line fill after the invalidation cycle. This is
illustrated by the asserted EADS# signal labeled "1" in
If the system asserts EADS# at the same time or after the first data in the line fill is
returned (in the same clock that the first RDY# or BRDY# is asserted or any
subsequent clock in the line fill) the data is read into the Intel
input buffers but it is not stored in the on-chip cache. This is illustrated by asserted
EADS# signal labeled "2" in
that initiated the cache fill cycle.
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Intel Quark SoC X1000 Core
Developer's Manual
216
Intel® Quark
Core
Address, Data and
Control Bus
Second-Level
Cache
Address, Data and
Control Bus
System Bus
External Bus
External
Master
Memory
Figure 104. The stale data is used to satisfy the request
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Intel Quark Core—Bus Operation
Figure 104.
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Quark SoC X1000 Core
October 2013
Order Number: 329679-001US
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