Cache Control; Write-Back Enhanced Intel Operating Modes; Cache Operating Modes - Intel Quark SoC X1000 Core Developer's Manual

Table 36.

Cache Operating Modes

CD NW
1
1
0
0
7.2

Cache Control

Control of the cache is provided by the CD and NW bits in CR0. CD enables and disables
the cache. NW controls memory write-throughs and invalidates.
The CD and NW bits define four operating modes of the on-chip cache, as given in
Table 36. These modes provide flexibility in how the on-chip cache is used.
CD=1, NW=1
The cache is completely disabled by setting CD=1 and NW=1 and then flushing the
cache. This mode may be useful for debugging programs in which it is important to
see all memory cycles at the pins. Writes that hit in the cache do not appear on the
external bus.
It is possible to use the on-chip cache as fast static RAM by "pre-loading" certain
memory areas into the cache and then setting CD=1 and NW=1. Pre-loading can
be done by careful choice of memory references with the cache turned on or by
using of the testability functions (see
page
"frozen" into the cache because fills and invalidates are disabled.
CD=1, NW=0
Cache fills are disabled but write-throughs and invalidates are enabled. This mode
is the same as if the KEN# pin was strapped high, disabling cache fills. Write-
throughs and invalidates still may occur to keep the cache valid. This mode is
useful when the software must disable the cache for a short period of time, and
then re-enable it without flushing the original contents.
CD=0, NW=1
Invalid. When CR0 is loaded with this bit configuration, a General Protection fault
with an error code of 0 occurs.
CD=0, NW=0
This is the normal operating mode.
Completely disabling the cache is a two-step process. First, CD and NW must be set to
1, and then the cache must be flushed. When the cache is not flushed, cache hits on
reads still occur and data is read from the cache.
7.2.1 Write-Back Enhanced Intel
Control and Operating Modes
The Write-Back Enhanced Intel
CR0.NW when the 1,1 state forces a cache-off condition after RESET and the 0,0 state
is the normal run state.
for write-back operation. The values in
write-back mode and some lines are in a write-through state.
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Intel Quark SoC X1000 Core
Developer's Manual
116
1 Cache fills disabled, write-through and invalidates disabled.
0 Cache fills disabled, write-through and invalidates enabled.
INVALID. When CR0 is loaded with this configuration of bits, a GP fault with error code of
1
0 is raised.
0 Cache fills enabled, write-through and invalidates enabled.
296). When the cache is turned off, the memory mapped by the cache is
®
Table 37
Operating Mode
Section B.1, "On-Chip Cache Testing" on
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Quark SoC X1000 Core Cache
Quark SoC X1000 Core retains the use of CR0.CD and
defines these control bits when the cache is enabled
Table 37 are also valid when the cache is in
®
Intel Quark Core—On-Chip Cache
October 2013
Order Number: 329679-001US