Intel Quark SoC X1000 Core Developer's Manual page 294

®
Table 95. Intel Quark SoC X1000 Core Pin Descriptions (Sheet 4 of 5)
Symbol Type
The Cache Flush input forces the Intel
FLUSH# I low and need only be asserted for one clock. FLUSH# is asynchronous but setup and hold times t20 and
t21 must be met for recognition in any specific clock.
The Page Write-Through and Page Cache Disable pins reflect the state of the page attribute bits, PWT
and PCD, in the page table entry, page directory entry or control register 3 (CR3) when paging is enabled.
PWT O When paging is disabled, the processor ignores the PCD and PWT bits and assumes they are zero for the
PCD O purpose of caching and driving PCD and PWT pins. PWT and PCD have the same timing as the cycle
definition pins (M/IO#, D/C#, and W/R#). PWT and PCD are active high and are not driven during bus
hold. PCD is masked by the cache disable bit (CD) in Control Register 0.
The Bus Size 16 and Bus Size 8 pins (bus sizing pins) cause the Intel
cycles to complete a request from devices that cannot provide or accept 32 bits of data in a single cycle.
BS16# I The bus sizing pins are sampled every clock. The state of these pins in the clock before ready is used by
BS8# I the Intel
internal pull-up resistors. These inputs must satisfy setup and hold times t14 and t15 for proper
operation.
Note:
When the Address Bit 20 Mask pin is asserted, the Intel
(A20) before performing a lookup to the internal cache or driving a memory cycle on the bus. A20M#
A20M# I
emulates the address wraparound at one Mbyte. A20M# is active low and should be asserted only when
the processor is in Real Mode. This pin is asynchronous but should meet setup and hold times t20 and t21
for recognition in any specific clock. For proper operation, A20M# should be sampled high at the falling
edge of RESET.
Test Clock is an input to the Intel
feature. TCK is used to clock state information and data into component on the rising edge of TCK on TMS
TCK I
and TDI, respectively. Data is clocked out of the part on the falling edge of TCK and TDO. TCK is provided
with an internal pull-up resistor.
Test Data Input is the serial input used to shift JTAG instructions and data into component. TDI is
TDI I sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR TAP controller states. During all
other tap controller states, TDI is a "don't care." TDI is provided with an internal pull-up resistor.
Test Data Output is the serial output used to shift JTAG instructions and data out of the component.
TDO O TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR TAP controller states. At all
other times TDO is driven to the high impedance state.
Test Mode Select is decoded by the JTAG TAP (Tap Access Port) to select the operation of the test logic.
TMS I TMS is sampled on the rising edge of TCK. To guarantee deterministic behavior of the TAP controller TMS
is provided with an internal pull-up resistor.
The Reserved input detects the presence of the in-circuit emulator, then powers down the core, and
Reserved# I three-states all outputs of the original processor, so that the original processor consumes very low
current. Reserved# is active low and sampled at all times, including after power-up and during reset.
The Floating-Point Error pin is driven active when a floating-point error occurs. FERR# is included for
FERR# O compatibility with systems using DOS type floating-point error reporting. FERR# does not go active when
FP errors are masked in FPU register. FERR# is active low, and is not floated during bus hold.
Note:
When the Ignore Numeric Error pin is asserted the processor ignores a numeric error and continue
executing non-control floating-point instructions, but FERR# is still activated by the processor. When
IGNNE# I
IGNNE# is deasserted, the processor freezes on a non-control floating-point instruction, when a previous
floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 is
set. IGNNE# is active low and is provided with a small internal pull-up resistor. IGNNE# is asynchronous
but setup and hold times t20 and t21 must be met to insure recognition on any specific clock.
®
Intel Quark SoC X1000 Core
Developer's Manual
294
PAGE CACHEABILITY
BUS SIZE CONTROL
®
Quark Core to determine the bus size. These signals are active low and are provided with
ADDRESS MASK
® ®
Intel Quark Core on Intel Quark SoC X1000 does not use the A20M# pin; it is tied to 1'b1.
TEST ACCESS PORT
®
Quark Core and provides the clocking function required by the JTAG
PERFORMANCE UPGRADE SUPPORT
NUMERIC ERROR REPORTING
®
The implementation of Intel
control the IGNNE# pin via a register; the default value of the register is 1'b0.
Intel
Name and Function
®
Quark Core to flush its entire internal cache. FLUSH# is active
®
Quark Core masks physical address bit 20
®
Quark Core on Intel Quark SoC X1000 provides the capability to
®
Quark Core—Signal Descriptions
®
Quark Core to run multiple bus
October 2013
Order Number: 329679-001US