Intel Quark SoC X1000 Core Developer's Manual page 278

Table 89. Clock Count Summary (Sheet 12 of 13)
Instruction
LTR = Load Task Register
From register
From memory
SGDT = Store Global Descriptor Table
SIDT = Store Interrupt Descriptor Table
SLDT = Store Local Descriptor Table
To register
To memory
SMSW = Store Machine Status Word
To register
To memory
STR = Store Task Register
To register
To memory
VERR = Verify Read Access
Register
Memory
VERW = Verify Write Access
To register
To memory
INTERRUPT INSTRUCTIONS
INTn = Interrupt Type n
INT3 = Interrupt Type 3
INTO = Interrupt 4 if Overflow Flag Set
Taken
Not Taken
BOUND = Interrupt 5 if Detect Value Out Range
If in range
If out of range
IRET = Interrupt Return
Real Mode/Virtual Mode
Protected Mode
To same level
To outer level
To nested task
(EFLAGS.NT=1)
Note: See
®
Intel Quark SoC X1000 Core
Developer's Manual
278
0000 1111 : 0000 0000 : 11 011 reg
0000 1111 : 0000 0000 : mod 011 r/m
0000 1111 : 0000 0001 : mod 000 r/m
0000 1111 : 0000 0001 : mod 001 r/m
0000 1111 : 0000 0000 : 11 000 reg
0000 1111 : 0000 0001 : mod 000 r/m
0000 1111 : 0000 0001 : 11 000 reg
0000 1111 : 0000 0001 : mod 100 r/m
0000 1111 : 0000 0000 : 11 001 r/m
0000 1111 : 0000 0000 : mod 001 r/m
0000 1111 : 0000 0000 : 11 100 r/m
0000 1111 : 0000 0000 : mod 100 r/m
0000 1111 : 0000 0000 : 11 101 r/m
0000 1111 : 0000 0000 : mod 101 r/m
1100 1101 : type
1100 1100
1100 1110
0110 0010 : mod reg r/m
1100 1111
Table 92 for notes and abbreviations for items in this table.
®
Intel Quark Core—Instruction Set Summary
Cache
Format
INT+4/0
INT+0
INT+2
INT+24
TS+32
Penalty
if
Notes
Hit Cache
Miss
20
20
10
2
2
3
2
3
2
3
11 3
11 7
11 3
11 7
RV/P, 21
21
21
3 21
7 7 21
7 21
15 8
20 11 9
36 19 9
4 9,10
October 2013
Order Number: 329679-001US