Data Test Register: Tr7; Tlb Write Test; Encoding Of Bit 4 Of Tr7 On Writes; Encoding Of Bit 4 Of Tr7 On Lookups - Intel Quark SoC X1000 Core Developer's Manual

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Testability—Intel Quark Core
B.2.2.2

Data Test Register: TR7

TR7 contains the information stored or read from the data block during a TLB test
operation. Before a TLB test write, TR7 contains the physical address and the page
attribute bits to be stored in the entry. After a TLB test lookup hit, TR7 contains the
physical address, page attributes, LRU bits and entry location from the access.
TR7 contains a 20-bit physical address (bits 31:12), PLD bit (bit 11), PWT bit (bit 10),
and three bits for the LRU bits (bits 9:7). The LRU bits in TR7 are only used during a
TLB lookup test. The functionality of TR7 bit 4 differs for TLB writes and lookups. The
encoding of bit 4 is defined in
(bits 3:2) to specify a TLB replacement pointer or the location of a TLB hit.
Table 100.
A replacement pointer is used during a TLB write. The pointer indicates which of the
four entries in an accessed set is to be written. The replacement pointer can be
specified to be the internal LRU bits or bits 3:2 in TR7. The source of the replacement
pointer is specified by TR7 bit 4. The encoding of bit 4 during a write is given by
Table 100.
Note that both testability writes and lookups affect the state of the internal LRU bits
regardless of the replacement pointer used. All TLB write operations (testability or
normal operation) cause the written entry to become the most recently used. For
example, during a testability write with the replacement pointer specified by TR7 bits
3:2, the indicated entry is written and that entry becomes the most recently used as
specified by the internal LRU bits.
There are two TLB testing operations: write entries into the TLB, and perform TLB
lookups.
Note that any time one TLB set contains the same linear address in more than one of
its entries, looking up that linear address gives unpredictable results. Therefore a single
linear address should not be written to one TLB set more than once.
Table 101.
B.2.3

TLB Write Test

To perform a TLB write TR7 must be loaded followed by a TR6 load. The register
operations must be performed in this order because the TLB operation is triggered by
the write to TR6.
TR7 is loaded with a 20-bit physical address and values for PCD and PWT to be written
to the data portion of the TLB. In addition, bit 4 of TR7 must be loaded to indicate
whether to use TR7 bits 3-2 or the internal LRU bits as the replacement pointer on the
TLB write operation. Note that the LRU bits in TR7 are not used in a write test.
October 2013
Order Number: 329679-001US
Table 100

Encoding of Bit 4 of TR7 on Writes

TR7 Bit 4 Replacement Pointer Used on TLB Write
0
1

Encoding of Bit 4 of TR7 on Lookups

TR7 Bit 4 Meaning after TLB Lookup Operation
0 TLB Lookup Resulted in a Miss
1 TLB Lookup Resulted in a Hit
and Table 101. Finally, TR7 contains two bits
Pseudo-LRU Replacement Pointer
Data Test Register Bits 3:2
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