Bus Operation; Data Transfer Mechanism; Memory And I/O Spaces; Byte Enables And Associated Data And Operand Bytes - Intel Quark SoC X1000 Core Developer's Manual

10.0

Bus Operation

When the internal cache of the Write-Back Enhanced Intel
configured in write-through mode, the processor bus operates in Standard Bus mode.
However, when the internal cache of the Write-Back Enhanced Intel
Core is configured in write-back mode, the bus then operates in the Enhanced Bus
mode, which is described in
10.1

Data Transfer Mechanism

All data transfers occur as a result of one or more bus cycles. Logical data operands of
byte, word and doubleword lengths may be transferred without restrictions on physical
address alignment. Data may be accessed at any byte boundary but two or three cycles
may be required for unaligned data transfers. See
for details.
The Intel
order address bits are provided by the address lines, A[31:2]. The byte enables,
BE[3:0]#, form the low-order address and provide linear selects for the four bytes of
the 32-bit address bus.
The byte enable outputs are asserted when their associated data bus bytes are
involved with the present bus cycle, as listed in
have a deasserted byte enable separating two or three asserted byte enables never
occur (see
Table 60.
Address bits A0 and A1 of the physical operand's base address can be created when
necessary. Use of the byte enables to create A0 and A1 is shown in
enables can also be decoded to generate BLE# (byte low enable) and BHE# (byte high
enable). These signals are needed to address 16-bit memory systems. (See
Section 10.1.3.)
10.1.1

Memory and I/O Spaces

Bus cycles may access physical memory space or I/O space. Peripheral devices in the
system can be either memory-mapped, I/O-mapped, or both. Physical memory
addresses range from 00000000H to FFFFFFFFH (4 gigabytes). I/O addresses range
from 00000000H to 0000FFFFH (64 Kbytes) for programmed I/O. (See
®
Intel Quark SoC X1000 Core
Developer's Manual
184
Section
®
Quark SoC X1000 Core address signals are split into two components. High-
Table 64). All other byte enable patterns are possible.

Byte Enables and Associated Data and Operand Bytes

Byte Enable Signal
BE0#
BE1#
BE2#
BE3#
Intel
®
10.4.
Section 10.1.2
Table 60. Byte enable patterns that
Associated Data Bus Signals
D[7:0] (byte 0–least significant)
D[15:8] (byte 1)
D[23:16] (byte 2)
D[31:24] (byte 3–most significant)
®
Quark Core—Bus Operation
Quark SoC X1000 Core is
®
Quark SoC X1000
and Section 10.1.5
Table 61. The byte
Figure 77.)
October 2013
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