® Intel Quark™ SoC X1000 Platform Design Guide (PDG) Revision 002US June 2014 Order Number: 330258-002US...
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® Intel Quark™ SoC X1000—Contents 21.6 Guidelines for Component Placement..............152 21.6.1 PHY Placement Recommendations............152 21.7 MDI Differential-Pair Trace Routing for LAN Design ..........154 21.8 Signal Trace Geometry ..................154 21.9 Trace Length and Symmetry ................157 21.10 Impedance Discontinuities ................157 21.11 Reducing Circuit Inductance ................
A Schottky Diode Circuit to Connect RTC External Battery..........90 RTCRST# External Circuit for the SoC RTC..............91 Example GPIO[7:0] Topology level shifted Guideline ............. 94 Generic GPIO[7:0] Topology Guideline ................ 94 Intel® Galileo Platform Power Delivery ............... 98 ® Intel Quark™ SoC X1000 Power-up Sequence ............99 platform_s5_pwrok generation.................
® Intel Quark™ SoC X1000—Contents Current Loop Radiation of a Transmission Line............109 Radiation Cancellation of a Differential Line ..............110 An Example of VR EMI Noise ..................111 VR Noise Can Result In Both SI and EMI Issues ............111 Simplified Voltage Regulator Module Circuit and VRM EMI Noise ........
® Contents—Intel Quark™ SoC X1000 104 Recommended Thermal Via Patterns................. 183 105 Stencil Design Recommendation ................184 106 Assembly Flow....................... 184 107 Typical Profile Band ....................185 ® Intel Quark™ SoC X1000 June 2014 Order Number: 330258-002US...
® Intel Quark™ SoC X1000—Contents Tables Platform Stack-up Parameter Values (Microstrip) ............18 Electrical Limits of LH Material Properties ..............20 Breakout Geometries for Various I/O Interfaces ............23 Max Root Square Sum (RSS) Length vs. Transfer Speed ..........25 This Guideline Supports the Following Configurations.............29 DDR3 Channel Signal Groups ..................30...
X1000 Platform Design Guide has been developed to ensure maximum flexibility for board designers while reducing the risk of board related issues. Design recommendations are based on Intel’s simulations and lab experience and are strongly recommended, if not necessary, to meet the timing and signal quality specifications.
® Stack-Up and PCB Considerations—Intel Quark™ SoC X1000 Stack-Up and PCB Considerations Note: Metric units are used in some sections in addition to the standard use of U.S. customary system of units (USCS). If there is a discrepancy between the metric and USCS units, assume the USCS unit is most accurate.
• The parameter values for internal and external traces are the final thickness and width after the motherboard materials are laminated, conductors plated, and etched. Intel uses these exact values to generate the associated electrical models for simulation. Figure 2.
® Stack-Up and PCB Considerations—Intel Quark™ SoC X1000 Table 1. Platform Stack-up Parameter Values (Microstrip) (Sheet 2 of 2) - Manufac- - Design/ + Design/ + Manufac- Typical Microstrip Units turing Material Material turing Value Value Value Tolerance Tolerance Tolerance...
FR4. However, if the limits are adhered to, then the risk of signal integrity problems due to the LH material is greatly reduced. Intel bases signal integrity analysis and validation on these ranges. Designers should also ensure the LH dielectric materials chosen meet all applicable thermal, mechanical and UL flammability requirements.
Calculating and comparing backward coupling coefficients is recommended to choose proper trace spacing in cases where the selected stack-up varies from the Intel recommendation. The coupling coefficients represent the source voltage percentage that is coupled to victim lines.
® Intel Quark™ SoC X1000—Stack-Up and PCB Considerations Figure 6. Single-ended Kb Diagram Figure 7. Differential Kb Diagram Single-Ended and Differential-Impedance Transmission Line Specifications Table 3 lists breakout trace geometries for various I/O interfaces. Breakout topologies are mainly decided by package ballout patterns and pitches. So similar geometries will be used for various stack-ups.
® Stack-Up and PCB Considerations—Intel Quark™ SoC X1000 Table 4 lists examples of single-ended and differential impedances specified for different interfaces. The microstrip single-ended impedance tolerance is ±15%. The stripline and dual-stripline single-ended impedance and differential impedance tolerance is ±10%. The microstrip differential-impedance tolerance is ±15%.
® Intel Quark™ SoC X1000—Stack-Up and PCB Considerations Figure 8. Common Glass Cloths Used in PCB Manufacture 1080 1080 2113 2113 2116 2116 1652 1652 7628 7628 Note: Weave types above are for illustration purposes only Figure 9. Inhomogeneous Nature of a PCB as Shown in this Cross-Section...
® Stack-Up and PCB Considerations—Intel Quark™ SoC X1000 Figure 10. Effect of Skew on Differential and Common Mode Signals Figure 11. Cross-Section of PCB Indicating Effect of PCB Fiber Weave Etching / Plating Impacts on Trace Geometries Resin Rich Dielectric...
® Intel Quark™ SoC X1000—Stack-Up and PCB Considerations edge of the board. Those lengths should not be considered in this analysis. The total length is the Root Square Sum of total vertical and horizontal lengths that run parallel to the weave: ...
® Stack-Up and PCB Considerations—Intel Quark™ SoC X1000 Figure 13. An Example of Zig-Zag Routing Figure 14. An Example of Slanted Routing 2.6.6 Image Rotation Another solution is to maintain an angle between the trace and the fiber weave pattern...
® Intel Quark™ SoC X1000—Stack-Up and PCB Considerations Figure 15. An Example of a PCB Cut Such That Its Edges are Rotated Relative to the Fiber Weave Pattern > Glass bundle alignment HVM variation 2.6.7 Using Alternate PCB Materials The fiber weave effect can also be minimized by using PCB material that exhibits less variation in the dielectric coefficient E between the epoxy and glass materials.
® DDR3 Memory Design Guidelines—Intel Quark™ SoC X1000 DDR3 Memory Design Guidelines Memory General Introduction ® Intel Quark™ SoC X1000 Customer Reference Board (codename Kips Bay) platforms support DDR3 memory technology. The CRB’s SoC memory interface supports a single- channel of DDR3 memory with 8-bit wide data and up to 2 ranks per channel at 800 MT/s.
It is recommended that all of the signals have solid GND referencing planes on both sides. Minimize the size of void if there are voids on reference planes. Memory Topology Guidelines ® This chapter presents the various DDR3 topologies possible with Intel Quark™ SoC X1000 platforms and associated constraints for PCB layout. Note: The SoC package length is labeled as "P1"...
® DDR3 Memory Design Guidelines—Intel Quark™ SoC X1000 3.3.1 Single Rank Fly-by Topology with Active VTT Termination The topology presented in this chapter is the basic DDR topology for 4 Layer PCB designs. For PCB stack-up information please refer to Chapter 2.0.
® Intel Quark™ SoC X1000—DDR3 Memory Design Guidelines Table 8. DQ/DQS Routing Guidelines and Settings for a Single Rank 4L Fly-by Design— PCB Type 3 (Sheet 2 of 2) Parameter Routing Guideline / Setting Trace Spacing (S2): Between adjacent data min = 10.0 mils...
® DDR3 Memory Design Guidelines—Intel Quark™ SoC X1000 Figure 18. ODT/CKE/CS - Control Routing Topology for a Single Rank 4L Fly-by Design - PCB Type 3 DRAM DRAM Breakin Breakin Package Breakout Breakin Breakout Breakout Main Main Breakin Breakin Termination...
® Intel Quark™ SoC X1000—DDR3 Memory Design Guidelines Table 9. Control - Routing Guidelines and Settings for a Single Rank 4L Fly-by Design— PCB Type 3 (Sheet 2 of 2) Parameter Routing Guideline / Setting Length matching between point-to-point CTRL signals and all CTRL = (CLK/CLKB - 50 mils) ±...
® DDR3 Memory Design Guidelines—Intel Quark™ SoC X1000 Table 10. Command Routing Guidelines and Settings for a Single Rank 4L Fly-by Design—PCB Type 3 (Sheet 2 of 2) Parameter Routing Guideline / Setting Trace Spacing (S1): min = min =...
188.8.131.52 ODT Signal Connectivity and Support For DDR3 memory-down design, Intel recommends ODT signals to be routed between SoC and DRAM devices on platform. This way, ODT timings at DRAM device can be fully controlled by the SoC.
3.4.1 SoC DDR Reference Voltage ® The Intel Quark™ SoC X1000 uses an internal circuitry to adjust the reference voltage used to qualify the logic levels on incoming DDR data bits. This capability is used to perform a vertical read data eye training. The DDR_VREF input allows supplying an external reference voltage, but in normal circumstances the internal reference voltage shall be used and DDR_VREF input shall be connected to GND.
In this case the ZQ calibration is performed in series - one ® rank at the time. The savings for Intel Quark™ SoC X1000 dual rank platforms by using this approach is 4 -> 2 precision resistors with four x8 DRAM devices, and is not as significant as for the products with wider data buses and more ranks.
® Intel Quark™ SoC X1000—DDR3 Memory Design Guidelines ® Intel Quark™ SoC X1000 June 2014 Order Number: 330258-002US...
® PCI Express* Design Guidelines—Intel Quark™ SoC X1000 PCI Express* Design Guidelines PCIe* General Introduction 4.1.1 Description ® The Intel Quark™ SoC X1000 SoC provides two PCI Express* root ports. The PCIe* root ports consist of one lane each configured as a 2x1 port. Each Root Port is PCIe* 2.0 compliant.
• Pull-up Wake# to VCC_SUS 3.3 via a 10-k? resistor. Note: If used, check with latest version of the Intel® Quark SoC x1000 Datasheet for maximum leakage specification on PCIE_WAKE# pin while selecting a pull up resistor in order to ensure Vih at SOC pin is satisfied.
® Intel Quark™ SoC X1000—PCI Express* Design Guidelines 4.3.1 Expansion Card Connector Topology The Design Guide recommendations are based on surface mount connectors that meet the insertion loss and return loss characteristics as specified in PCI Express* CEM 2.0 Specification. These guidelines include all trace routing on the board and the breakout region.
® Intel Quark™ SoC X1000—PCI Express* Design Guidelines Place the caps for P and N of a diff pair at exact same location Symmetrically route the P and N from SOC to the Cap. Symmetrically route the P and N from cap to the Connector Stagger the caps of different differential pairs Table 20.
® Universal Serial Bus 2.0 Design Guidelines—Intel Quark™ SoC X1000 Universal Serial Bus 2.0 Design Guidelines USB 2.0 General Introduction 5.1.1 Description ® The Intel Quark™ SoC X1000 supports up to 2 USB 2.0 Host ports that can be used to connect to high-speed, full-speed, and low-speed USB devices via an EHCI controller and/or a OHCI USB controller.
® Intel Quark™ SoC X1000—Universal Serial Bus 2.0 Design Guidelines USB 2.0 Signal Descriptions 5.2.1 Signal Groups Table 21. Signal Groups Group Signal Name Description USBH0_DP, USBH0_DN DATA USBH1_DP, USBH1_DN Universal Serial Bus Port Differential Pairs USBD_DP, USBD_DN USBH0_OC_B OVERCURRENT...
USB port is protected by only one overcurrent pin. Operation with more than one overcurrent pin mapped to a port is undefined. See the ® Intel Quark SoC X1000 Datasheet for more details. USB 2.0 Topology Guidelines 5.3.1 External Topologies The external topology refers to the routing of USB signals to a microUSB connector.
USB Connector Recommendations ® Proper connector choice is critical to ensure adequate USB signal quality. For the Intel Quark™ SoC X1000 the initial recommendation is the use of single USB connectors, empirical data has shown that quad-stack USB connectors may add interference causing poor USB signal quality.
® Universal Serial Bus 2.0 Design Guidelines—Intel Quark™ SoC X1000 5.3.3 Daughter Card The best way to provide internal support for USB is to use a daughter card and cable assembly. This allows the placement of the EMI/ESD suppression components right at the USB connector where they will be the most effective.
(droop) and dynamic detach flyback protection. These two types require both bulk capacitance (droop) and filtering capacitance (for dynamic detach flyback voltage filtering). Intel recommends the following: • Minimize the inductance and resistance between the coupling capacitors and the USB ports.
® I2C* Interface Design Guidelines—Intel Quark™ SoC X1000 C* Interface Design Guidelines C* General Introduction 6.1.1 Description ® There is a single I C* controller in Intel Quark™ SoC X1000. The interface is a two- wire I C serial interface consisting of a serial data line and a serial clock, only 3.3v operation is supported.
® Intel Quark™ SoC X1000—I2C* Interface Design Guidelines C* Topology Guidelines 6.3.1 General Design Considerations • I C clock and data signals require pull-up resistors. The pull-up resistor size is dependent on the bus capacitive load (this includes all device leakage currents).
® I2C* Interface Design Guidelines—Intel Quark™ SoC X1000 C* Connectivity The I C interface is primarily to support various sensors which may have different bandwidth requirements on the platform. Figure 30. Example of Devices on I C* Bus Sensor Sensors ®...
® Intel Quark™ SoC X1000—I2C* Interface Design Guidelines C* Additional Guidelines System designers must consider the total bus capacitance, which includes both SoC and device pin capacitance and board trace length capacitance when designing I C bus. The total bus capacitance must not exceed 400 pF.
® SDIO Interface Design Guidelines—Intel Quark™ SoC X1000 SDIO Interface Design Guidelines SDIO General Introduction 7.1.1 Description ® Intel Quark™ SoC X1000 implements a single SDIO interface that is only intended for general-purpose connections, such as SD cards. It supports SDIO card specification 3.0 and the MMC specification 3.31, 4.2, and 4.41.
® Intel Quark™ SoC X1000—SDIO Interface Design Guidelines SDIO Topology Guidelines This section contains information and details for layout and routing guidelines for the SDIO interfaces. Figure 31. SDIO Topology with Connector Connector Breakout CFIOHVTEW NO RCOMP Table 29. SDIO Layout Guideline...
® UART Interface Design Guidelines—Intel Quark™ SoC X1000 UART Interface Design Guidelines General Introduction 8.1.1 Description ® The Intel Quark™ SoC X1000 SoC integrates two UART controllers. Each supports up to a max 2.76 Mbit/s. The interfaces support 3.3V only. The controllers can be used in the low-speed, full-speed, and high-speed modes.
® General Purpose SPI Interface Design Guidelines—Intel Quark™ SoC X1000 General Purpose SPI Interface Design Guidelines General Introduction 9.1.1 Description The two general-purpose SPI interfaces support various devices which use serial protocols for transferring data such as sensors on the platform.
® General Purpose SPI Interface Design Guidelines—Intel Quark™ SoC X1000 Table 36. SPI0_MISO Breakout Trace Spacing(S3): Between GPIO 4.2 mil 10 mil 10 mil 4.2 mil and other signals Trace Segment Length 0.5" max 0.1" - 3.0" 0.1" - 0.8"...
® General Purpose SPI Interface Design Guidelines—Intel Quark™ SoC X1000 Terminating Unused SPI Signals If the SPI functionality is not utilized, the signals should be terminated properly with external pull-up or pull-down resistors. Table 39. SOC SPI Internal Pull Up/ Pull Down...
In the full-clock integration mode, a 25 MHz crystal oscillator ® provides the input clock to the Intel Quark™ SoC X1000 integrated clock controller and SoC generates the output clocks that are required by all the platform components.
It is critical that this XTAL clock is of good quality and has minimal interference to ensure correct locking of the internal PLL. Intel is not validating use of an external clock buffer oscillator connection to XTAL pins.
® Intel Quark™ SoC X1000—Platform Clocks Design Guidelines 10.3.1.1 Differential Routing Considerations When routing differential clocks, note the following recommendations: • Ground referencing is preferred. However, differential clocks can be routed referenced to other planes through the use of stitching capacitors to provide the appropriate decoupling where the signal crosses planes.
® Platform Clocks Design Guidelines—Intel Quark™ SoC X1000 Table 42. iClock (Single-ended Clocks) ® For the Intel Quark™ SoC X1000 use case, one of the flex clocks, RMII_REF_CLK_OUT clock, is used as a reference to the RMII. This clock is routed to the PHY and also back the SoC integrated MAC.
® Intel Quark™ SoC X1000—Platform Clocks Design Guidelines 10.4.1 Crystal External Load Capacitor Requirements The 25 MHz crystal is physically tuned to operate within the specified frequency range and ppm tolerance with a certain expected capacitive load present. The expected external capacitive load to be used (Ce) consists of the crystal capacitive load plus the pin and trace capacitances.
® Platform Clocks Design Guidelines—Intel Quark™ SoC X1000 Figure 38. 25 MHz Crystal External Load Capacitor Parameters S O C D river O scillator P in 2-3pF 1M B ias R esistor 25M H z T ra ce 2 -1 0p F...
® Intel Quark™ SoC X1000—Platform Clocks Design Guidelines ® Intel Quark™ SoC X1000 June 2014 Order Number: 330258-002US...
® Legacy SPI serial output data from Intel Quark™ SoC X1000 to LSPI_MOSI Data the SPI flash device. ® Legacy SPI serial input data from the SPI flash device to Intel LSPI_MISO Data Quark™ SoC X1000. ® LSPI_CLK Clock Legacy SPI Clock output from Intel Quark™...
Quark™ SoC X1000 SPI interface. The Legacy SPI flash must be ® directly connected to the Intel Quark™ SoC X1000 Legacy SPI bus in all SKUs. Also, refer to the Serial Flash vendor documentation for additional Serial Flash specific design considerations.
OEMs must fully validate any SPI flash device to ensure compatibility with their platforms. This should not be considered a complete list of SPI vendors and is not an indication of Intel approved devices or vendors. Please contact your preferred flash vendor directly to determine if they have a compatible device.
® Intel Quark™ SoC X1000—SPI Flash Design Guidelines ® Intel Quark™ SoC X1000 June 2014 Order Number: 330258-002US...
® RTC Design Guidelines—Intel Quark™ SoC X1000 12.0 RTC Design Guidelines 12.1 Real Time Clock General Introduction 12.1.1 Description ® the Intel Quark™ SoC X1000 contains a real time clock (RTC) with 256 bytes of battery-backed SRAM. The internal RTC module provides two key functions: keeping date and time and storing system data in its RAM when the system is powered down.
VCC3P3_S5 is active whenever the system is plugged-in. Vbatt is voltage provided by the battery and is optional. VccRTC, RTCX1, and RTCX2 are Intel SoC pins. VccRTC powers SoC RTC well. RTCX1 is the input to the internal oscillator. RTCX1 can be driven by external clock generator to desired frequency.
RTC circuit. Some recommendations are: • Reduce trace capacitance by minimizing the RTC trace length. Intel SoC recommends a trace length less than 1 inch on each branch (from crystal’s terminal to RTCXn ball).
® RTC Design Guidelines—Intel Quark™ SoC X1000 The following example illustrates the use of the practical values C1, C2 in the case that theoretical values cannot guarantee the accuracy of the RTC in low temperature condition: Example: According to a required 12 pF load capacitance of a typical crystal that is used with the SoC, the calculated value of C1 = C2 is 10 pF at room temperature (25 °C) to yield an...
® Intel Quark™ SoC X1000—RTC Design Guidelines Figure 43. A Schottky Diode Circuit to Connect RTC External Battery 1.4V drop 0.5V drop Schottky Diodes VCC3P3_S5 VCCRTC 0.1uF 240 1K The ESR limits the charge 3.6K current and is negligible for the RTC input current.
® Intel Quark™ SoC X1000—RTC Design Guidelines 12.6 RTC-Well Input Strap Requirements All RTC-well inputs must be either pulled up to VCCRTC3P3 or pulled down to ground while in the G3 state. RTCRST_B, when configured as shown in Figure 44 meets this requirement.
Asynchronous Signals General Introduction 13.1.1 Description This section describes the topologies and layout recommendations for the ® asynchronous signals. Refer to the Intel Quark SoC X1000 Datasheet for more details. 13.2 Asynchronous Signal Descriptions 13.2.1 Signal Groups Table 48. Asynchronous Legacy Signal Group...
14.0 Platform Power Delivery Requirements ® This chapter provides the recommended way to power up the Intel Quark™ SoC X1000 from the platform. It is assumed the platform provides a single input voltage (5v) from which we derive three primary platform voltages (1.0v, 3.3v, and 1.5v). Each of these primary platform voltages are split and subsequently enabled in a specific sequence to ensure proper SoC functioning.
Figure 48. At ® each step after the S5_PG signal asserts, the Intel Quark™ SoC X1000 internal power management block enables the subsequent power rails through a process of handshaking. These enable signals are utilized on the platform to control the FET switches which control the S3 and S0 power rails.
® Platform Reset Considerations—Intel Quark™ SoC X1000 15.0 Platform Reset Considerations 15.1 Platform Reset General Introduction 15.1.1 Description Platform reset signals is a group of reset signals that control power on sequence, power management, and provide proper reset to all components on the platform. This chapter provides detailed guideline on how to generate and use platform reset signal to ensure functionality of the platform.
15.3.6 PWRBTN# Usage Model ® The Power Button signal (PWRBTN#) on the Intel Quark™ SoC X1000 can be connected directly to the power button on the system’s front panel header. When system power button is pressed, PWRBTN# should be pulled low. The SoC has 2.5ms or more of internal debounce logic on this pin, external debouncing circuit is not required.
® Platform Reset Considerations—Intel Quark™ SoC X1000 15.3.8 Power-well Isolation Control Signal Requirements 15.3.9 platform_s5_pwrok Generation The platform_s5_pwrok signal is generated from the platform regulator V1P5 or equivalent detection logic. The signal should be generated based on the v1p5 rail achieving 90% of its nominal value Figure 49.
® Intel Quark™ SoC X1000—Platform Reset Considerations 15.3.14 Additional Power Sequencing Considerations It is possible that on rare occasions, wake events can cause the system to immediately wake after entering in S3 power state. In such circumstances it is possible that the SoC will generate the same duration pulse widths on the v3p3_s0_en, v1p5_s0_en and v1p0_s0_en as during normal cold boot.
Description ® Critical Low Speed Signals are identified as critical input signals from the Intel Quark™ SoC X1000 that are low frequency but have huge impact to system functionality or stability. Glitches on these signals may cause system to behave in unpredicted manners or cause unpredicted system shutdown or reset.
® Intel Quark™ SoC X1000—Critical Low Speed Signals Design Guidelines 16.3 Additional Guidelines All critical signals must stay away from potential glitch or noise sources on the platform. It is recommended to keep all critical signal traces a minimum of 15 mils away from any clock or high speed differential signals with >...
® Electromagnetic Interference—Intel Quark™ SoC X1000 17.0 Electromagnetic Interference 17.1 Electromagnetic Interference (EMI) General Introduction 17.1.1 Description The main component of EMI is a radiated electromagnetic wave, which consists of both electric (E-fields) and magnetic (H-fields) waves traveling together and oriented perpendicular to each other.
® Intel Quark™ SoC X1000—Electromagnetic Interference Figure 51. Time Domain Capture of Exerciser Operation It is recommended to use a write-read-erasure sequence with a random data pattern. While a repeated pattern is very reproducible, it will produce far worse and unrealistic EMI levels than a typical real-world application.
® Electromagnetic Interference—Intel Quark™ SoC X1000 17.3 EMI Source 17.3.1 Current Loop Radiation Current loop radiation is formed by the forward current and return current. For example, the current loop of signals travelling on a microstrip line is shown in the following figure.
® Intel Quark™ SoC X1000—Electromagnetic Interference Figure 53. Radiation Cancellation of a Differential Line 17.3.2 Voltage Regulator Module Current Loop Radiation The noise from voltage regulator module (VRM) is typically around 50~300MHz.The two noise peaks at 125 and 250 MHz shown in Figure 54 are an example.
® Electromagnetic Interference—Intel Quark™ SoC X1000 Figure 54. An Example of VR EMI Noise P latform noise Figure 55. VR Noise Can Result In Both SI and EMI Issues Figure 56. Simplified Voltage Regulator Module Circuit and VRM EMI Noise It is also found that the EMI noise is correlated with the ringing at the phase node(Vx).
® Intel Quark™ SoC X1000—Electromagnetic Interference Figure 57. The Vx Ripples with/without Gate Resistors (Left: without gate resistor/ Right: with gate resistor) Besides the 50 to 300MHz EMI noise, the hundreds kHz switching noise can result in signal integrity issues if the noise is coupled to IO nets in proximity. It is critical to trap the noise within the input loop and minimize the noise propagation.
® Electromagnetic Interference—Intel Quark™ SoC X1000 Figure 58. Emission from a Differential line with Various Skews As much as 35dB of As much as 35dB of increased radiation increased radiation can been seen with can been seen with 150ps of skew...
® Intel Quark™ SoC X1000—Electromagnetic Interference Figure 59. Changing Referencing, Lack of Referencing, Void-crossing, and Split-crossing are Not Recommended 17.4.2 Avoid Signal Traces Too Close to the Edges of Planes Signal traces routed too close to the edges of referencing planes excite edge radiations.
® Electromagnetic Interference—Intel Quark™ SoC X1000 Figure 61. Keep-out Zone Determined Around IO and Other Connectors 17.4.4 EMI Mitigation through Stitching and Decoupling Capacitors EMI emission can be mitigated with capacitors, which create low-impedance paths for signals or noises to pass through. These paths could minimize current loop areas or change plane resonant frequencies.
® Intel Quark™ SoC X1000—Electromagnetic Interference 184.108.40.206 Stitching Capacitors Stitching capacitors are used to create return current path for signal traces with different references. Using stitching capacitors for split-crossing is one example. The separated reference planes have different voltages. They are, therefore, not able to be merged.
® Intel Quark™ SoC X1000—Electromagnetic Interference Figure 65. Stitching Capacitors Should be Close to Traces 220.127.116.11 Decoupling Capacitors Decoupling capacitors are used to mitigate the noise on power rails or planes. Noise sources on power rails or planes are mainly from voltage regulators and IC chipsets.
® Electromagnetic Interference—Intel Quark™ SoC X1000 Figure 67. Decoupling Capacitors with Vias Other noise sources are from the signal traces adjacent to power planes. Power plane could be considered as an antenna radiating noises coupled from these traces. Populating decoupling capacitors around the planes is a way of mitigation.
IO for maximum effect. 18.104.22.168 USB Common Mode Choke Recommendation Intel recommends implementing a common-mode choke (CMC) footprint for each USB 2.0 pair. Please refer to Section 17.4.6 for USB 2.0 common mode choke recommendations.
® Electromagnetic Interference—Intel Quark™ SoC X1000 means that the signal quality must be checked for low-speed, full-speed, and high- speed USB operation. • Further common mode choke information can be found on the high-speed USB Platform Design Guides available at www.usb.org.
® Intel Quark™ SoC X1000—Electromagnetic Interference The frequency modulation in the time-domain results in a frequency-domain energy redistribution of the constant-frequency clock harmonics. The shape of the spectral energy distribution of the SSC is determined by the time-domain modulation profile, while the energy distribution width is determined be the modulation amount ( ...
Quark™ SoC X1000 17.4.9 Memory Down Memory down PCB layout may be challenging to minimize EMI/RFI. Intel recommends the following guidance: • Place DRAMs closest to CPU. • Clocks should be at least 3X the trace width away from other traces.
17.4.10 Cable/Adaptor Shielding During EMI measurement, one may find some EMI violations are from the IOs such as USB and HDMI. Intel recommend check the cable/adaptor shielding quality before implementing a PCB solution, common mode choke for example. Figure 73 shows an example.
® Electromagnetic Interference—Intel Quark™ SoC X1000 17.5 Design Checklist Items This section provides a checklist that should be reviewed during the design process. This checklist has been developed over time and experience to reduce the possibility of unwanted emissions. The checklist is shown below. Not every suggestion is 100% effective;...
® Intel Quark™ SoC X1000—Electromagnetic Interference Table 58. I/O Routing Review Checklist ITEM DESCRIPTION All I/O connectors have been provided with a low impedance bond to chassis for their 171-1 shield structure. 171-2 All non-ground nets routed externally, should have a filter present.
® Electrostatic Discharge (ESD)—Intel Quark™ SoC X1000 18.0 Electrostatic Discharge (ESD) 18.1 Electrostatic Discharge (ESD) General Introduction 18.1.1 Description All electronic equipment that is sold into the European Union and mutually recognized countries, must possess the CE mark which designates it has passed a required set of test standards;...
® Intel Quark™ SoC X1000—Electrostatic Discharge (ESD) Figure 74. IEC 61000-4-2 ESD Waveform 18.1.2 Reference Specifications Title Location http://www.iec.ch/ IEC 61000-4-2 18.2 ESD Protection Selection criteria for discreet ESD protection devices must include consideration for the electrical constraints of the interface needing protection. Many discreet semiconductor ESD manufacturers now manufacturer devices for specific low- and high-speed interfaces.
18.2.1 ESD Ground-Fill Reducing sensitivity to Electrostatic Discharge (ESD) to ensure Intel products comply with ESD standards can be a time and cost intensive effort. This section recommends changes to the printed circuit board design that will reduce ESD sensitivity by implementing a low impedance ESD current path to ground, thereby, reducing the coupling to sensitive circuitry.
300 mils apart, close to the board’s edge. 18.2.3 USB ESD Diode Recommendation Intel recommends placing ESD protection devices for each USB 2.0 data pair. Selection of USB 2.0 ESD diode should be particularly careful and should be different due to different speeds. Please refer to Section 18.3.1...
ESD noise even when ESD diodes are not activated. The peak voltage and current may be significantly reduced. Due to the low-pass nature of this filter, Intel does not recommend applying this filter to high-speed links. This filter may degrade signal integrity of high speed signaling.
® Intel Quark™ SoC X1000—Electrostatic Discharge (ESD) The effectiveness of this series RC-filter is shown in Figure 79. The magnitude of the sharp peak is effectively reduced by 75% with the series RC filter. The filter has significant impacts on ESD robustness, since this sharp peak contains huge amounts of high-frequency components and is typically the origination of most problematic symptoms in the system.
ESD injections. This significantly reduces the required time and cost to solve ESD-related issues. A test approach to assess net sensitivities on Intel platforms has been developed. In this approach, Transmission line pulser (TLP) is employed to generate a sharp and short pulse to emulate ESD noise.
18.3.2 USB 2.0 ESD Protection Diode Vendors ESD suppression is always recommended by Intel. However Intel does not recommend a specific part/device or circuit for ESD suppression because each solution is board/ chassis/usage model specific.The following vendors manufacture ESD protection Diode for USB2.0 which conform to the IEC 61000-4-2 standard.
® Electrostatic Discharge (ESD)—Intel Quark™ SoC X1000 CalMicro: http://www.calmicro.com ONSemi: http://www.onsemi.com Philips: http://www.philips.com Protek Devices: http://www.protekdevices.com SEMTECH: http://www.semtech.com STMicro: http://www.st.com Note: This is not an extensive list. There may be others. Please check with your preferred vendor to determine if a compatible device is available.
® Intel Quark™ SoC X1000—Electrostatic Discharge (ESD) 18.4 Design Checklist Items This section provides a checklist that should be reviewed during the design process. This checklist has been developed over time and experience to reduce the possibility of unwanted ESD risk. The checklist is shown below. Not every suggestion is 100% effective;...
Platform Debug and Test Hooks General Introduction 19.1.1 Description Intel is committed to reducing debug time and cost for OEMs and system integrators. Many debug features and test hooks can be designed into the platform to help reduce ® these factors. The following section provides an overview of the Intel Quark™...
19.4.1 Test Points Requirements Intel recommends users at least provide through-hole vias in a location that is probe accessible (avoid location that is blocked by thermal solutions or other mechanical components) and/or pull-up/pull-down resistors, for all the test points so that Intel would be able to access them when debug by Intel is required.
VREG Controller’s data sheet https://commu- nities.intel.com/ ® community/makers/ Intel Quark SoC X1000 Datasheet documentation/ quarkdocuments 20.2 DFT Configuration, Connectivity, Block Diagram DFT probe points can be placed anywhere on the trace. It is preferred to place test beads directly on the trace or vias. However, if beads can not be placed directly on the trace, the stub to the bead should be less than 50 mils (1.27 mm), shown in...
® Intel Quark™ SoC X1000—Design for Testability (DFT) Figure 86. Example of Test Bead on a Stub (Not Preferred) Stub Stub <50 <50 mils mils Figure 87. Example of Differential Test Bead with Matched Placement Table 63. Bead Parameters (Sheet 1 of 2)
® Design for Testability (DFT)—Intel Quark™ SoC X1000 Table 63. Bead Parameters (Sheet 2 of 2) Recommendation Parameter Units Beads formed over Beads placed on solder-mask-openings existing vias Typical Bead-to-Component Pitch mils requirement Typical flying probe diameter mils Notes: Bead-to-Bead pitch and bead-to-component requirements are based on the bed-of-nails or probe capabilities.
® LAN Design Considerations and Guidelines—Intel Quark™ SoC X1000 21.0 LAN Design Considerations and Guidelines ® The Intel Quark™ SoC X1000 incorporates an integrated 10/100 Mbps MAC controller that can be used with an external PHY shown in Figure 90. Its bus master capabilities...
® Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines ® Table 64. MDIO Data Signals on the Intel Quark™ SoC X1000 Group PHY Signal Name SOC Signal Name Description MAC_0 Data MDIO MAC0 MDIO MDIO data MAC_1 Data MDIO MAC1_MDIO MDIO data Table 65.
21.2 Platform LAN Design Guidelines These sections provide recommendations for selecting components and connecting ® special pins. For Ethernet designs, the main elements are Intel Quark™ SoC X1000, PHYs, a magnetics modules, RJ-45 connectors and a clock source. 21.2.1 General Design Considerations for PHYs...
® Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines 22.214.171.124 Clock Source All designs require a 50 MHz clock source. The PHY uses the 50 MHz source to generate internal clocks for both the PHY circuits and the RMII interface. SoC generates this 50Mhz reference clock internally and is passed out of the SoC for routing to the PHY and back to the MAC reference clock port.
More details may be obtained from the Datasheet. Intel has a software utility called EEupdate that is used to program the SPI Flash images in development or production line environments. A copy of this program can be obtained through your Intel representative.
® Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines Figure 91. LED Hardware Configuration Yellow 330 ohm LED2 Green LED1 Green VCC3P3 330 ohm LED0 126.96.36.199 RBIAS RBIAS requires external resistor connection to bias the internal analog section of the device.
® LAN Design Considerations and Guidelines—Intel Quark™ SoC X1000 ® 21.3 Intel Quark™ SoC X1000 – MDIO/RMII LOM Design Guidelines This section contains guidelines on how to implement a SoC/PHY single solution on a system motherboard. It should not be treated as a specification, and the system designer must ensure through simulations or other techniques that the system meets the specified timings.
® Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines 21.4 General Layout Guidelines PHY interface signals must be carefully routed on the motherboard to meet the timing and signal quality requirements of their respective interface specifications. The following are some general guidelines that should be followed in designing a LAN solution.
® LAN Design Considerations and Guidelines—Intel Quark™ SoC X1000 Figure 93. PLC Placement: At Least One Inch from I/O Backplane Figure 94. Effect of LAN Device Placed Too Close To a RJ-45 Connector or Chassis Opening ® Intel Quark™ SoC X1000...
® Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines 21.7 MDI Differential-Pair Trace Routing for LAN Design Trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible to decrease interference from other signals, including those propagated through power and ground planes.
Refer to Table 69 for examples of microstrip trace geometries for common circuit board materials. Intel® Quark™ SoC designs without LAN switch can range up to ~8 inches. Refer to Table 69 for trace length information.
® LAN Design Considerations and Guidelines—Intel Quark™ SoC X1000 21.9 Trace Length and Symmetry The differential traces should be equal in total length to within 10 mils (0.254 mm) per segment within each pair and as symmetrical as possible. Asymmetrical and unequal length traces in the differential pairs contribute to common mode noise.
® Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines 21.11 Reducing Circuit Inductance Traces should be routed over a continuous reference plane with no interruptions. If there are vacant areas on a reference or power plane, the signal conductors should not cross the vacant area.
® LAN Design Considerations and Guidelines—Intel Quark™ SoC X1000 If the transition is from power-referenced layer to a ground-referenced layer or from one voltage-power referenced layer to a different voltage-power referenced layer, then stitching capacitors should be used within 40 mils of the transition.
® LAN Design Considerations and Guidelines—Intel Quark™ SoC X1000 21.14 Traces for Decoupling Capacitors Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long and thin traces are more inductive and reduce the intended effect of decoupling capacitors.
® Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines Table 70. Capacitor Stuffing Option Recommended Values Capacitors Value C3, C4 4.7 µF or 10 µF C1, C2, C5, C6 470 pF to 0.1 µF The placement of C1 through C6 may also differ for each board design (in other words, not all of the capacitors may need to be populated).
® LAN Design Considerations and Guidelines—Intel Quark™ SoC X1000 21.16 Light Emitting Diodes The device has three high-current outputs to directly drive LEDs for link, activity and speed indication. Since LEDs are likely to be integral to a magnetics module, take care to route the LED traces away from potential sources of EMI noise.
® Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines 5. Using a low-quality magnetics module. 6. Reusing an out-of-date physical layer schematic in a Ethernet silicon design. The terminations and decoupling can be different from one PHY to another. 7. Incorrect differential trace impedances. It is important to have about a 100-...
® LAN Design Considerations and Guidelines—Intel Quark™ SoC X1000 21.21 Power Delivery In general planes should be used to deliver 3.3 Vdc and the Core voltage. Not using planes can cause resistive voltage drop and/or inductive voltage drop (due to transient or static currents).
® Intel Quark™ SoC X1000—LAN Design Considerations and Guidelines Table 72. MAC0_RXDATA<1:0>; MAC0_RXDV Breakout Trace Spacing(S2): Between 4.2 mil 10 mil 10 mil 4.2 mil RMII Signals Trace Spacing(S3): Between 4.2 mil 10 mil 10 mil 4.2 mil RMII and other signals Trace Segment Length 0.5"...
There are a broad range of Wireless modules available suited to different regulatory, performance and user requirements. This chapter shall discuss choice of antenna ® materials, placement options and coexistence considerations for Intel Quark™ SoC X1000-based designs. Co-existence of multiple wireless modules and their antennas, among themselves and with the other systems and parts in the device can become a major problem if not considered in the initial stages of design.
22.2.3 WiFi Module There is a broad offering of Intel and third-party WiFi modules supporting various 802.11 standards. Offerings are also differentiated by the number of inputs and outputs. In addition to cost, system integrators can keep in mind antenna placement options and wireless performance/quality requirements while making choices.
® Wireless Modules and Antenna Design Guidelines—Intel Quark™ SoC X1000 22.2.4 WiFi Module Connector Types As WiFi modules are mounted on the platform, connectors plugging into them will add to the total z-height. OEM’s can select connectors of low z-heights to keep the total z- height down.
® Intel Quark™ SoC X1000—Wireless Modules and Antenna Design Guidelines 22.2.7 Antenna Cabling The antenna cable is a lossy structure and hence needs to be as short as possible. Design choices can help reduce the cable length to the absolute minimum achievable.Studies have shown that acceptable performance metrics (loss/VSWR) can...
® General Differential Signals Design Guidelines—Intel Quark™ SoC X1000 Appendix A General Differential Signals Design Guidelines Introduction The guidelines in this chapter are to improve routing for differential signals, such as PCIe* or USB. The signal routing, via placement and bend optimization examples below apply to all high speed interfaces.
® Intel Quark™ SoC X1000—General Differential Signals Design Guidelines before transitioning to a different layer. At any via transition the n/p mismatch for the entire route preceding the via cannot exceed 15mils. • When trace length matching occurs, the matching should be made as close as...
® General Differential Signals Design Guidelines—Intel Quark™ SoC X1000 Figure A-3. Etch Located Within a Pad Example These Segments of Trace are These Segments of Trace are Considered to be Part of the Pad Considered to be Part of the Pad Figure A-4.
® Intel Quark™ SoC X1000—General Differential Signals Design Guidelines General Differential Optimization Guidelines A.4.1 Breakout Example and Guidelines Maintain differential routing rules in package breakout areas. Figure A-5. SoC Package Breakout Example Guidelines are as follows: • Differential-pair pitch is measured from the center of each trace in the differential-pair.
® General Differential Signals Design Guidelines—Intel Quark™ SoC X1000 Figure A-6. Differential-Pair Spacing Diagram Pitch PTPS Figure A-7. Symmetrical and Non-Symmetrical Routing Example Avoid: Non-symmetrical Routing Preferred: Symmetrical Routing A.4.2 Via Placement and Via Usage Optimization • Vias impact the overall loss and jitter budget. Route signals with a minimal number of vias.
® Intel Quark™ SoC X1000—General Differential Signals Design Guidelines Figure A-8. Via Pair Example Figure A-9. Example - Via Placement 1 • The symmetric via pattern in Figure A-10 below minimizes crosstalk between 2 differential pair, therefore the recommendation is to implement the pattern according to area availability.
® General Differential Signals Design Guidelines—Intel Quark™ SoC X1000 Figure A-10. Example - Via Placement 2 • For differential interfaces it is recommended 1:1 ratio of signal to GND via everywhere it is possible (Figure A-11). Figure A-11. Package Breakout Example - Via Placement 3 A.4.3...
® Intel Quark™ SoC X1000—General Differential Signals Design Guidelines Figure A-12. Acceptable Bends vs. Tight Bends Example P referred - N o t C o nsid ered “T ight B en d s” A v o id ! - “T ig h t B en d s”...
® General Differential Signals Design Guidelines—Intel Quark™ SoC X1000 • Differential signals should not cross any plane splits or voids. However, it may be necessary for a trace to be partially routed over a via anti-pad void in the chipset escape area.
® Exposed Pad* (e-Pad*) Design and SMT Assembly Guide—Intel Quark™ SoC X1000 Appendix B Exposed Pad* (e-Pad*) Design and SMT Assembly Guide Overview This section provides general information about ePAD and SMT assemblies. Chip packages have exposed die pads on the bottom of each package to provide electrical interconnections with the printed circuit board.
® Intel Quark™ SoC X1000—Exposed Pad* (e-Pad*) Design and SMT Assembly Guide Figure 102. Typical ePAD* Land Pattern Figure 103. Typical Thermal Pad and Via Recommendations Note: Encroached and uncapped via configurations have voids less than the maximum allowable void percentage. Uncapped via provides a path for trapped air to escape during the reflow soldering process.
® Exposed Pad* (e-Pad*) Design and SMT Assembly Guide—Intel Quark™ SoC X1000 Figure 104. Recommended Thermal Via Patterns Board Mounting Guidelines The following are general recommendations for mounting a QFN-48 device on the PCB. This should serve as the starting point in assembly process development and it is recommended that the process should be developed based on past experience in mounting standard, non-thermally/electrically enhanced packages.
Time from 25 °C to Peak: 240 – 360 s Intel recommends a maximum solder void of 50% after reflow. Note: Contact your Intel representative for any designs unable to meet the recommended guidance for E-pad implementation. § § ®...