Burst Control; Burst Ready Input (Brdy#); Burst Last Output (Blast#); Interrupt Signals - Intel Quark SoC X1000 Core Developer's Manual

RDY# is active low, and is not provided with an internal pull-up resistor. This input must
satisfy setup and hold times t
9.2.7

Burst Control

9.2.7.1

Burst Ready Input (BRDY#)

BRDY# performs the same function during a burst cycle that RDY# performs during a
non-burst cycle. BRDY# indicates that the external system has presented valid data on
the data pins in response to a read or that the external system has accepted the Intel
Quark SoC X1000 Core data in response to a write. BRDY# is ignored when the bus is
idle and at the end of the first clock in a bus cycle.
During a burst cycle, BRDY# is sampled each clock. If it is active, the data presented
on the data bus pins is strobed into the Intel
negated during the second through last data cycles in the burst, but address lines
A[3:2] and the byte enables change to reflect the next data item expected by the
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Intel Quark SoC X1000 Core.
If RDY# is returned simultaneously with BRDY#, BRDY# is ignored and the burst cycle
is prematurely aborted. An additional complete bus cycle is initiated after an aborted
burst cycle if the cache line fill was not complete. BRDY# is treated as a normal ready
for the last data cycle in a burst transfer or for non-burstable cycles (see
for burst cycle timing).
BRDY# is active low and is provided with a small internal pull-up resistor. BRDY# must
satisfy the setup and hold times t
9.2.7.2

Burst Last Output (BLAST#)

BLAST# indicates that the next time BRDY# is returned it will be treated as a normal
RDY#, terminating the line fill or other multiple-data-cycle transfer. BLAST# is active
for all bus cycles regardless of whether they are cacheable or not. This pin is active low
and is not driven during bus hold.
9.2.8

Interrupt Signals

The interrupt signals can interrupt or suspend execution of the processor's instruction
stream.
9.2.8.1

Reset Input (RESET)

The RESET input must be used at power-up to initialize the processor. RESET forces the
processor to begin execution at a known state. The processor cannot begin execution of
instructions until at least 1 ms after V
specifications. The RESET pin should remain active during this time to ensure proper
processor operation. However, for warm boot-ups RESET should remain active for at
least 15 CLK periods. RESET is active high. RESET is asynchronous but must meet
setup and hold times t
RESET returns SMBASE to the default value of 30000H. If SMBASE relocation is not
used, RESET can be used as the only reset (see
Mode (SMM)
The Intel
sampled active at the falling edge of RESET.
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Intel Quark SoC X1000 Core
Developer's Manual
154
16
and t
20 21
Architectures").
®
Quark SoC X1000 Core is placed in the Power Down Mode if RESERVED# is
Intel
and t for proper chip operation.
17
®
Quark SoC X1000 Core. ADS# is
and t .
16 17
and CLK reach their proper DC and AC
CC
for recognition in any specific clock.
Chapter 8.0, "System Management
®
Quark Core—Hardware Interface
Section 10.3.2
October 2013
Order Number: 329679-001US
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