Snoop Cycle Overlaying A Line-Fill Cycle - Intel Quark SoC X1000 Core Developer's Manual

In Figure
Back Enhanced Intel
EADS#, but delays the snoop write-back cycle until the line fill is completed, because
the line fill shown in
clock after ADS#. In the clock after AHOLD is asserted, the Write-Back Enhanced
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Intel Quark SoC X1000 Core floats the address bus (not the Byte Enables). Hence,
the memory controller must determine burst addresses in this period. The chipset must
comprehend the special ordering required by all burst sequences of the Write-Back
Enhanced Intel
the write-back cycle completes.
If AHOLD continues to be asserted over the forced write-back cycle, the memory
controller also must supply the write-back addresses to the memory. The Write-Back
Enhanced Intel
sequence of 0-4-8-C.
In general, if the snoop cycle overlays any burst cycle (not necessarily a line-fill cycle)
the snoop write-back is delayed because of the on-going burst cycle. First, the burst
cycle goes to completion and only then does the snoop write-back cycle start.
Figure 114. Snoop Cycle Overlaying a Line-Fill Cycle
CLK
AHOLD
EADS#
INV
HITM#
A31–A4
A3–A2
ADS#
BLAST#
CACHE#
BRDY#
W/R#
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Intel Quark SoC X1000 Core
Developer's Manual
232
114, the snoop to an M-state line causes a snoop write-back cycle. The Write-
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Quark SoC X1000 Core asserts HITM# two clocks after the
Figure 114 is a burst cycle. In this figure, AHOLD is asserted one
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Quark SoC X1000 Core. HITM# is guaranteed to remain asserted until
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Quark SoC X1000 Core always runs the write-back with an address
1 2 3 4
†
Fill
0
†
To Processor
‡
Write-back from Processor
Intel
5 6 7 8 9
‡
Fill
0
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Quark Core—Bus Operation
10 11 12 13
4 8 C
242202-151
October 2013
Order Number: 329679-001US