Architectural Overview; Internal Architecture; System Architecture; Memory Organization - Intel Quark SoC X1000 Core Developer's Manual

3.0

Architectural Overview

3.1

Internal Architecture

The Intel
and cache and floating-point units. The Intel
sizing for the external data bus; that is, the bus size can be specified as 8-, 16-, or 32-
bits wide.
Note: The implementation of Intel
dynamic bus sizing. Bus width is fixed at 32 bits.
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Intel Quark Core functional units are listed below:
• Bus Interface Unit (BIU)
• Cache Unit
• Instruction Prefetch Unit
• Instruction Decode Unit
• Control Unit
• Integer (Datapath) Unit
• Floating-Point Unit
• Segmentation Unit
• Paging Unit
For further details, see Chapter 3 in the Intel
Reference Manual.
3.2

System Architecture

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Intel Quark Core System Architecture includes the following:
•

Memory Organization

• I/O Space
• Addressing Modes
• Data Types
• Interrupts
3.3 Memory Organization
Memory on the Intel
16-bit quantities (words), and 32-bit quantities (dwords). Words are stored in two
consecutive bytes in memory with the low-order byte at the lowest address, the high
order byte at the high address. Dwords are stored in four consecutive bytes in memory
with the low-order byte at the lowest address, the high-order byte at the highest
address. The address of a word or dword is the byte address of the low-order byte.
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Intel Quark SoC X1000 Core
Developer's Manual
22
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Quark Core has a 32-bit architecture with on-chip memory management
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Quark Core on Intel
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Quark SoC X1000 Core is divided up into 8-bit quantities (bytes),
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Intel Quark Core—Architectural Overview
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Quark Core also supports dynamic bus
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Quark SoC X1000 does not support
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Quark SoC X1000 Core Hardware
Order Number: 329679-001US
October 2013