Pseudo-Locked Cycles; Locked Bus Cycle - Intel Quark SoC X1000 Core Developer's Manual

Figure 99.

Locked Bus Cycle

CLK
ADS#
A31–A2
M/IO#
D/C#
BE3#–BE0#
W/R#
RDY#
DATA
LOCK#
10.3.7

Pseudo-Locked Cycles

Pseudo-locked cycles assure that no other master is given control of the bus during
operand transfers that take more than one bus cycle.
For the Intel
cache line fills.
Pseudo-locked transfers are indicated by the PLOCK# pin. The memory operands must
be aligned for correct operation of a pseudo-locked cycle.
PLOCK# need not be examined during burst reads. A 64-bit aligned operand can be
retrieved in one burst (note that this is only valid in systems that do not interrupt
bursts).
The system must examine PLOCK# during 64-bit writes since the Intel
X1000 Core cannot burst write more than 32 bits. However, burst can be used within
each 32-bit write cycle if BS8# or BS16# is asserted. BLAST is de-asserted in response
to BS8# or BS16#. A 64-bit write is driven out as two non-burst bus cycles. BLAST# is
asserted during both 32-bit writes, because a burst is not possible. PLOCK# is asserted
during the first write to indicate that another write follows. This behavior is shown in
Figure 100.
The first cycle of a 64-bit floating-point write is the only case in which both PLOCK#
and BLAST# are asserted. Normally PLOCK# and BLAST# are the inverse of each other.
During all of the cycles in which PLOCK# is asserted, HOLD is not acknowledged until
the cycle completes. This results in a large HOLD latency, especially when BS8# or
BS16# is asserted. To reduce the HOLD latency during these cycles, windows are
available between transfers to allow HOLD to be acknowledged during non-cacheable
code prefetches. PLOCK# is asserted because BLAST# is deasserted, but PLOCK# is
ignored and HOLD is recognized during the prefetch.
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Intel Quark SoC X1000 Core
Developer's Manual
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Quark SoC X1000 Core, examples include 64-bit description loads and
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Quark Core—Bus Operation
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Quark SoC
October 2013
Order Number: 329679-001US