8- And 16-Bit Cycles; Interrupted Burst Cycle With Non-Obvious Order Of Addresses - Intel Quark SoC X1000 Core Developer's Manual

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Bus Operation—Intel Quark Core
Figure 96.

Interrupted Burst Cycle with Non-Obvious Order of Addresses

CLK
ADS#
A31–A2
RDY#
BRDY#
KEN#
BLAST#
DATA
10.3.5

8- and 16-Bit Cycles

The Intel
the BS16# and BS8# inputs. BS16# and BS8# allow the external system to specify, on
a cycle-by-cycle basis, whether the addressed component can supply 8, 16 or 32 bits.
BS16# and BS8# can be used in burst cycles as well as non-burst cycles. If both
BS16# and BS8# are asserted for any bus cycle, the Intel
responds as if only BS8# is asserted.
The timing of BS16# and BS8# is the same as that of KEN#. BS16# and BS8# must be
asserted before the first RDY# or BRDY# is asserted. Asserting BS16# and BS8# can
force the Intel
have been only a single 32-bit cycle. BS8# and BS16# may change the state of
BLAST# when they force subsequent cycles from the transfer.
Figure 97
run two extra cycles to complete a transfer. The Intel
request for 24 bits of information. The external system asserts BS8#, indicating that
only eight bits of data can be supplied per cycle. The Intel
issues two extra cycles to complete the transfer.
October 2013
Order Number: 329679-001US
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Quark SoC X1000 Core supports both 16- and 8-bit external buses through
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Quark SoC X1000 Core to run additional cycles to complete what would
shows an example in which BS8# forces the Intel
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Quark SoC X1000 Core issues a
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Quark SoC X1000 Core
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Quark SoC X1000 Core
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Intel Quark SoC X1000 Core
Developer's Manual
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