Pin States During Reset - Intel Quark SoC X1000 Core Developer's Manual

Figure 72.

Pin States During RESET

CLK
RESET
AHOLD
FLUSH#
Sync)
FLUSH#
(Async)
A20M#
(Sync)
A20M#
(Async)
ADS#
BREQ
A31:4,
MIO#,
BLAST
A3, A2,
PLOCK
D/C#, W/R#,
PCHK#
LOCK#
D[31:0]
HLDA
SMIACT#
WB/WT#
CACHE#
HITM#
See notes on next page.
®
Intel Quark SoC X1000 Core
Developer's Manual
172
T T T
X X X
At least 15 CLK periods
(1)
20
T
(7)
(9)
(10)
®
Intel Quark Core—Hardware Interface
T T T
X
I
(8)
17
~2 CLK if no self-test
(1)
20
~2 CLK if no self-test
20
T
(6)
(4)
(5)
(2)
(3)
U
NDEFINED
U
NDEFINED
Order Number: 329679-001US
T T
I I I
October 2013