Address Bit 20 Mask (A20M#); Enhanced Bus Features; Cacheability (Cache#); Differences Between Cache# And Pcd - Intel Quark SoC X1000 Core Developer's Manual

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Hardware Interface—Intel
BS16# and BS8# are active low and are provided with small internal pull-up resistors.
BS16# and BS8# must satisfy the setup and hold times t
operation.
9.2.16

Address Bit 20 Mask (A20M#)

Note: The implementation of Intel
A20M# pin; it is tied to 1'b1.
Asserting the A20M# input causes the Intel
address bit 20 before performing a lookup in the internal cache and before driving a
memory cycle to the outside world. When A20M# is asserted, the Intel
X1000 Core emulates the 1-Mbyte address wraparound. A20M# is active low and must
be asserted only when the processor is in Real Mode. A20M# is not defined in Protected
Mode. A20M# is asynchronous but should meet setup and hold times t
recognition in any specific clock. For correct operation of the chip, A20M# should not be
active at the falling edge of RESET.
A20M# exhibits a minimum 4 clock latency, from time of assertion to masking of the
A20 bit. A20M# is ignored during cache invalidation cycles. I/O writes require A20M#
to be asserted a minimum of 2 clocks prior to RDY being returned for the I/O write. This
ensures recognition of the address mask before the Intel
begins executing the instruction following OUT. If A20M# is asserted after the ADS# of
a data cycle, the A20 address signal is not masked during this cycle but is masked in
the next cycle. During a prefetch (cacheable or not), if A20M# is asserted after the first
ADS#, A20 is not masked for the duration of the prefetch even if BS16# or BS8# is
asserted.
9.2.17 Write-Back Enhanced Intel
Other Enhanced Bus Features
This section describes the pins that interface with the system to support the Enhanced
Bus mode/write-back cache features at system level.
9.2.17.1

Cacheability (CACHE#)

The CACHE# output indicates the internal cacheability on read cycles and a burst write-
back on write cycles. CACHE# is asserted for cacheable reads, cacheable code fetches
and write-backs. It is driven inactive for non-cacheable reads, special cycles, I/O cycles
and write-through cycles. This is different from the PCD (page cache disable) pin. The
operational differences between CACHE# and PCD are listed in
for operational differences between CACHE# and other Intel
signals.
Table 50. Differences between CACHE# and PCD (Sheet 1 of 2)
Bus Operation
Replacement write-back
Notes:
1. Includes line fills and non-cacheable reads. During locked read cycles CACHE# is inactive. The non-
cacheable reads may or may not be burst.
2. Due to the non-allocate on write policy, this includes both cacheable and non-cacheable writes. PCD
distinguishes between the two, but CACHE# does not.
3. This behavior is the same as the existing specification of the Intel
through mode.
October 2013
Order Number: 329679-001US
Quark Core
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Quark Core on Intel
(1)
All reads
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Quark SoC X1000 does not use the
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Quark SoC X1000 Core to mask physical
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Quark SoC X1000 Core
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Quark SoC X1000 Core Signals and
CACHE#
(3)
same as PCD
low
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and t for proper chip
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Quark SoC
and t for
20 21
Table 50. See Table 51
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Quark SoC X1000 Core
PCD
(3)
same as PCD
low
Quark SoC X1000 Core in write-
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Intel Quark SoC X1000 Core
Developer's Manual
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