Condition Code Interpretation After Fprem And Fprem1 Instructions; Floating-Point Condition Code Interpretation - Intel Quark SoC X1000 Core Developer's Manual

Table 14.

Condition Code Interpretation after FPREM and FPREM1 Instructions

C2
1
0
Table 15.

Floating-Point Condition Code Interpretation

Instruction
FPREM, FPREM1
FCOM, FCOMP, FCOMPP, FTST,
FUCOM, FUCOMP, FUCOMPP,
FICOM, FICOMP
FXAM
FCHS, FABS, FXCH, FINCTOP,
FDECTOP, Constant loads,
FXTRACT, FLD, FILD, FBLD, FSTP
(ext real)
FIST, FBSTP, FRNDINT, FST, FSTP,
FADD, FMUL, FDIV, FDIVR, FSUB,
FSUBR, FSCALE, FSQRT, FPATAN,
F2XM1, FYL2X, FYL2XP1
FPTAN, FSIN, FCOS, FSINCOS
FLDENV, FRSTOR
FINIT
FLDCW, FSTENV, FSTCW, FSTSW,
FCLEX, FSAVE
Notes:
1. When both IE and SF bits of status word are set, indicating a stack exception, this bit distinguishes
between stack overflow (C1 = 1) and underflow (C1 = 0).
2. Reduction: If FPREM or FPREM1 produces a remainder that is less than the modulus, reduction is complete.
When reduction is incomplete, the value at the top of the stack is a partial remainder, which can be used as
input to further reduction. For FPTAN, FSIN, FCOS, and FSINCOS, the reduction bit is set if the operand at
the top of the stack is too large. In this case, the original operand remains at the top of the stack.
3. Roundup: When the PE bit of the status word is set, this bit indicates whether the last rounding in the
instruction was upward.
4. UNDEFINED: Do not rely on finding any specific value in these bits. See
Software Compatibility" on page
®
Intel Quark SoC X1000 Core
Developer's Manual
56
Condition Code
C3 C1 C0
X X X
Q1 Q0 Q2
0 0 0
0 1 0
1 0 0
1 1 0
0 0 1
0 1 1
1 0 1
1 1 1
C0 (S)
Three least significant bits of quotient (See
Q2
Result of comparison (see
Operand class (see
63.
®
Intel Quark Core—System Register Organization
Interpretation after FPREM and FPREM1
Incomplete Reduction:
further interaction required for complete reduction
Q MOD8
0
1
2
3 C0, C3, and C1 contain the three
least-significant bits of the quotient
4
5
6
7
C3 (Z)
Q0
Table 16)
Table 17)
UNDEFINED
UNDEFINED Roundup or O/U#
UNDEFINED
O/U#, if C2 = 1
Each bit loaded from memory
Clears these bits
UNDEFINED
Complete Reduction:
C1 (A) C2 (C)
Reduction
Table 14.)
0 = complete
Q1 or O/U# 1 = incomplete
Operand is not
Zero or O/U#
comparable
Sign or O/U# Operand class
Zero or O/U# UNDEFINED
UNDEFINED
Reduction
Roundup or
0 = complete
1 = incomplete
Section 4.8, "Reserved Bits and
October 2013
Order Number: 329679-001US