Snoop Under Boff - Intel Quark SoC X1000 Core Developer's Manual

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Bus Operation—Intel Quark Core
If there is a snoop hit to a different line from the line being replaced, and if the
replacement write-back cycle is burst, the replacement cycle goes to completion. Only
then is the snoop write-back cycle initiated.
If the replacement write-back cycle is a non-burst cycle, and if there is a snoop hit to
the same line as the line being replaced, it fractures the replacement write-back cycle
after RDY# is asserted for the current non-burst transfer. The snoop write-back cycle is
reordered in front of the fractured replacement write-back cycle and is completed
under HITM#. However, after AHOLD is deasserted, the replacement write-back cycle is
not completed.
If there is a snoop hit to a line that is different from the one being replaced, the non-
burst replacement write-back cycle is fractured, and the snoop write-back cycle is
reordered ahead of the replacement write-back cycle. After the snoop write-back is
completed, the replacement write-back cycle continues.
10.4.3.4

Snoop under BOFF#

BOFF# is capable of fracturing any transfer, burst or non-burst. The output pins (see
Table 67
floated in the clock period following the assertion of BOFF#. If the system snoop hits a
modified line using BOFF#, the snoop write-back cycle is reordered ahead of the
current cycle. BOFF# must be de-asserted for the processor to perform a snoop write-
back cycle and resume the fractured cycle. The fractured cycle resumes with a new
ADS# and begins with the first uncompleted transfer. Snoops are permitted under
BOFF#, but write-back cycles are not started until BOFF# is de-asserted. Consequently,
multiple snoop cycles can occur under a continuously asserted BOFF#, but only up to
the first asserted HITM#.
10.4.3.4.1 Snoop under BOFF# during Cache Line Fill
As shown in
fill cycle. The system begins snooping by driving EADS# and INV in clock six. The
assertion of HITM# in clock eight indicates that the snoop cycle hit a modified line and
the cache line is written back to memory. The assertion of HITM# in clock eight and
CACHE# and ADS# in clock ten identifies the beginning of the snoop write-back cycle.
ADS# is guaranteed to be asserted no sooner than two clock periods after the assertion
of HITM#. Write-back cycles always use the four-doubleword address sequence of 0-4-
8-C (burst or non-burst). The snoop write-back cycle begins upon the de-assertion of
BOFF# with HITM# asserted throughout the duration of the snoop write-back cycle.
If the snoop cycle hits a line that is different from the line being filled, the cache line fill
resumes after the snoop write-back cycle completes, as shown in
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and Table 71) of the Write-Back Enhanced Intel
Figure 117, BOFF# fractures the second transfer of a non-burst cache line-
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Quark SoC X1000 Core are
Figure 117.
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Intel Quark SoC X1000 Core
Developer's Manual
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