Double Fault; Floating-Point Interrupt Vectors; Interrupt Vectors Used By Fpu - Intel Quark SoC X1000 Core Developer's Manual

3.7.8

Double Fault

A Double Fault (exception 8) results when the Intel
to invoke an exception service routine for the segment exceptions (10, 11, 12 or 13),
but in the process of doing so, detects an exception other than a Page Fault (exception
14).
A Double Fault (exception 8) will also be generated when the Intel
Core attempts to invoke the Page Fault (exception 14) service routine, and detects an
exception other than a second Page Fault. In any functional system, the entire Page
Fault service routine must remain "present" in memory.
When a Double Fault occurs, the Intel
service routine for exception 8.
3.7.9

Floating-Point Interrupt Vectors

Several interrupt vectors of the Intel
exceptional conditions while executing numeric programs in either real or protected
mode. Table 8
Table 8.

Interrupt Vectors Used by FPU

Interrupt Number
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Intel Quark SoC X1000 Core
Developer's Manual
38
shows these interrupts and their causes.
A Floating-Point instruction was encountered when EM or TS of the Intel
SoC X1000 Core control register zero (CR0) was set. EM = 1 indicates that
7 software emulation of the instruction is required. When TS is set, either a Floating-
Point or WAIT instruction causes interrupt 7. This indicates that the current FPU
context may not belong to the current task.
The first word or doubleword of a numeric operand is not entirely within the limit
of its segment. The return address pushed onto the stack of the exception handler
13 points at the Floating-Point instruction that caused the exception, including any
prefixes. The FPU has not executed this instruction; the instruction pointer and
data pointer register refer to a previous, correctly executed instruction.
The previous numerics instruction caused an unmasked exception. The address of
the faulty instruction and the address of its operand are stored in the instruction
pointer and data pointer registers. Only Floating-Point and WAIT instructions can
cause this interrupt. The Intel
16
onto the stack of the exception handler points to a WAIT or Floating-Point
instruction (including prefixes). This instruction can be restarted after clearing the
exception condition in the FPU. The FNINIT, FNCLEX, FNSTSW, FNSTENV, and
FNSAVE instructions can not cause this interrupt.
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Intel Quark Core—Architectural Overview
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Quark SoC X1000 Core attempts
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Quark SoC X1000 Core invokes the exception
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Quark SoC X1000 Core are used to report
Cause of Interrupt
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Quark SoC X1000 Core return address pushed
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Quark SoC X1000
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Quark
October 2013
Order Number: 329679-001US