Cache Flushing (Overlaid Smram) - Intel Quark SoC X1000 Core Developer's Manual

System Management Mode (SMM) Architectures—Intel
If SMRAM is overlaid with normal memory space, additional system design features are
needed to ensure that cache coherency is maintained.
requirements for entering and exiting the SMM when the SMRAM is overlaid with
normal memory space.
Table 48.

Cache Flushing (Overlaid SMRAM)

Normal Memory
Cacheable
WT or WB
WT or WB
If SMI# and FLUSH# are asserted together, the Write-Back Enhanced Intel
X1000 Core guarantees that FLUSH# is recognized first, followed by the SMI#. If the
cache is configured in the write-back mode, the modified lines are written back to the
normal user space, followed by the two special cycles. The SMI# is then recognized and
the transition to SMM occurs, as shown in
Cache flushing during SMM exit is accomplished by asserting the FLUSH# pin after the
SMIACT# pin is deasserted (within 1 CLK). To guarantee this behavior, follow the
constraints on setup and hold timings for the interaction of FLUSH# and SMIACT# as
specified for the Write-Back Enhanced Intel
The WBINVD instruction should not be used to flush the cache when exiting SMM.
Instead, the FLUSH# pin should be asserted after the SMIACT# pin is deasserted
(within one CLK). The cache coherency requirements associated with SMM and write-
through vs. write-back caches also apply to second-level cache control designs. The
appropriate second-level cache flushing also is required upon entering and exiting the
SMM.
Note: The implementation of Intel
second-level cache.
Figure 68. Write-Back Enhanced Intel
Overlaid SMRAM upon Entry and Exit of Cached SMM
Flash Cache
SMI#
SMIACT#
FLUSH#
October 2013
Order Number: 329679-001US
SMRAM Cacheable
No No
No WT
No
WT
®
Quark Core on Intel
®
Quark SoC X1000 Core Cache Flushing for
Write-
State
Back
Slave
Cycles
Cache must
be empty
®
Quark Core
Table 48
FLUSH Entering
SMM
No
No
Yes
Yes
Figure 68.
®
Quark SoC X1000 Core.
®
Quark SoC X1000 does not support
SMM
Handler
RSM
lists the cache flushing
FLUSH Exiting
SMM
No
Yes
No
Yes
®
Quark SoC
State Normal
Resume Cycle
Cache must
be empty
A5240-01
®
Intel Quark SoC X1000 Core
Developer's Manual
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